/*
 * Copyright (c) [2020], MediaTek Inc. All rights reserved.
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. and/or its licensors.
 * Except as otherwise provided in the applicable licensing terms with
 * MediaTek Inc. and/or its licensors, any reproduction, modification, use or
 * disclosure of MediaTek Software, and information contained herein, in whole
 * or in part, shall be strictly prohibited.
*/
//[File]            : bn0_wf_mib_top.h
//[Revision time]   : Fri Aug 31 11:01:27 2018
//[Description]     : This file is auto generated by CODA
//[Copyright]       : Copyright (C) 2018 Mediatek Incorportion. All rights reserved.

#ifndef __BN0_WF_MIB_TOP_REGS_H__
#define __BN0_WF_MIB_TOP_REGS_H__

#include "hal_common.h"

#ifdef __cplusplus
extern "C" {
#endif


//****************************************************************************
//
//                     BN0_WF_MIB_TOP CR Definitions                     
//
//****************************************************************************

#define BN0_WF_MIB_TOP_BASE                                    0x820ED000

#define BN0_WF_MIB_TOP_M0SCR0_ADDR                             (BN0_WF_MIB_TOP_BASE + 0x00) // D000
#define BN0_WF_MIB_TOP_M0PBSCR_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x04) // D004
#define BN0_WF_MIB_TOP_M0SCR1_ADDR                             (BN0_WF_MIB_TOP_BASE + 0x08) // D008
#define BN0_WF_MIB_TOP_M0MISCCR_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x00c) // D00C
#define BN0_WF_MIB_TOP_M0SDR0_ADDR                             (BN0_WF_MIB_TOP_BASE + 0x10) // D010
#define BN0_WF_MIB_TOP_M0SDR3_ADDR                             (BN0_WF_MIB_TOP_BASE + 0x14) // D014
#define BN0_WF_MIB_TOP_M0SDR4_ADDR                             (BN0_WF_MIB_TOP_BASE + 0x18) // D018
#define BN0_WF_MIB_TOP_M0SDR5_ADDR                             (BN0_WF_MIB_TOP_BASE + 0x1C) // D01C
#define BN0_WF_MIB_TOP_M0SDR6_ADDR                             (BN0_WF_MIB_TOP_BASE + 0x20) // D020
#define BN0_WF_MIB_TOP_M0SDR7_ADDR                             (BN0_WF_MIB_TOP_BASE + 0x24) // D024
#define BN0_WF_MIB_TOP_M0SDR8_ADDR                             (BN0_WF_MIB_TOP_BASE + 0x28) // D028
#define BN0_WF_MIB_TOP_M0SDR9_ADDR                             (BN0_WF_MIB_TOP_BASE + 0x2C) // D02C
#define BN0_WF_MIB_TOP_M0SDR10_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x30) // D030
#define BN0_WF_MIB_TOP_M0SDR11_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x34) // D034
#define BN0_WF_MIB_TOP_M0SDR12_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x38) // D038
#define BN0_WF_MIB_TOP_M0SDR13_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x3C) // D03C
#define BN0_WF_MIB_TOP_M0SDR14_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x40) // D040
#define BN0_WF_MIB_TOP_M0SDR15_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x44) // D044
#define BN0_WF_MIB_TOP_M0SDR16_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x48) // D048
#define BN0_WF_MIB_TOP_M0SDR17_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x4C) // D04C
#define BN0_WF_MIB_TOP_M0SDR18_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x50) // D050
#define BN0_WF_MIB_TOP_M0SDR19_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x54) // D054
#define BN0_WF_MIB_TOP_M0SDR20_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x58) // D058
#define BN0_WF_MIB_TOP_M0SDR21_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x5C) // D05C
#define BN0_WF_MIB_TOP_M0SDR22_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x60) // D060
#define BN0_WF_MIB_TOP_M0SDR23_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x64) // D064
#define BN0_WF_MIB_TOP_M0SDR24_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x68) // D068
#define BN0_WF_MIB_TOP_M0SDR25_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x6C) // D06C
#define BN0_WF_MIB_TOP_M0SDR26_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x70) // D070
#define BN0_WF_MIB_TOP_M0SDR27_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x74) // D074
#define BN0_WF_MIB_TOP_M0SDR28_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x78) // D078
#define BN0_WF_MIB_TOP_M0SDR30_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x80) // D080
#define BN0_WF_MIB_TOP_M0SDR31_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x84) // D084
#define BN0_WF_MIB_TOP_M0SDR32_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x88) // D088
#define BN0_WF_MIB_TOP_M0SDR33_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x8C) // D08C
#define BN0_WF_MIB_TOP_M0SDR34_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x90) // D090
#define BN0_WF_MIB_TOP_M0SDR35_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x94) // D094
#define BN0_WF_MIB_TOP_M0SDR36_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x98) // D098
#define BN0_WF_MIB_TOP_M0SDR37_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x9C) // D09C
#define BN0_WF_MIB_TOP_M0DR0_ADDR                              (BN0_WF_MIB_TOP_BASE + 0xA0) // D0A0
#define BN0_WF_MIB_TOP_M0DR1_ADDR                              (BN0_WF_MIB_TOP_BASE + 0xA4) // D0A4
#define BN0_WF_MIB_TOP_M0DR2_ADDR                              (BN0_WF_MIB_TOP_BASE + 0xA8) // D0A8
#define BN0_WF_MIB_TOP_M0DR3_ADDR                              (BN0_WF_MIB_TOP_BASE + 0xAC) // D0AC
#define BN0_WF_MIB_TOP_M0DR4_ADDR                              (BN0_WF_MIB_TOP_BASE + 0xB0) // D0B0
#define BN0_WF_MIB_TOP_M0DR5_ADDR                              (BN0_WF_MIB_TOP_BASE + 0xB4) // D0B4
#define BN0_WF_MIB_TOP_M0DR6_ADDR                              (BN0_WF_MIB_TOP_BASE + 0xB8) // D0B8
#define BN0_WF_MIB_TOP_M0DR7_ADDR                              (BN0_WF_MIB_TOP_BASE + 0xBC) // D0BC
#define BN0_WF_MIB_TOP_M0DR8_ADDR                              (BN0_WF_MIB_TOP_BASE + 0XC0) // D0C0
#define BN0_WF_MIB_TOP_M0DR9_ADDR                              (BN0_WF_MIB_TOP_BASE + 0XC4) // D0C4
#define BN0_WF_MIB_TOP_M0DR10_ADDR                             (BN0_WF_MIB_TOP_BASE + 0XC8) // D0C8
#define BN0_WF_MIB_TOP_M0DR11_ADDR                             (BN0_WF_MIB_TOP_BASE + 0XCC) // D0CC
#define BN0_WF_MIB_TOP_M0SDR38_ADDR                            (BN0_WF_MIB_TOP_BASE + 0xD0) // D0D0
#define BN0_WF_MIB_TOP_M0SDR39_ADDR                            (BN0_WF_MIB_TOP_BASE + 0xD4) // D0D4
#define BN0_WF_MIB_TOP_M0SDR40_ADDR                            (BN0_WF_MIB_TOP_BASE + 0xD8) // D0D8
#define BN0_WF_MIB_TOP_M0SDR41_ADDR                            (BN0_WF_MIB_TOP_BASE + 0xDC) // D0DC
#define BN0_WF_MIB_TOP_M0SDR42_ADDR                            (BN0_WF_MIB_TOP_BASE + 0xE0) // D0E0
#define BN0_WF_MIB_TOP_M0SDR43_ADDR                            (BN0_WF_MIB_TOP_BASE + 0xE4) // D0E4
#define BN0_WF_MIB_TOP_M0SDR44_ADDR                            (BN0_WF_MIB_TOP_BASE + 0xE8) // D0E8
#define BN0_WF_MIB_TOP_M0SDR45_ADDR                            (BN0_WF_MIB_TOP_BASE + 0xEC) // D0EC
#define BN0_WF_MIB_TOP_M0SDR46_ADDR                            (BN0_WF_MIB_TOP_BASE + 0xF0) // D0F0
#define BN0_WF_MIB_TOP_M0SDR47_ADDR                            (BN0_WF_MIB_TOP_BASE + 0xF4) // D0F4
#define BN0_WF_MIB_TOP_M0SDR48_ADDR                            (BN0_WF_MIB_TOP_BASE + 0xF8) // D0F8
#define BN0_WF_MIB_TOP_M0SDR49_ADDR                            (BN0_WF_MIB_TOP_BASE + 0xFC) // D0FC
#define BN0_WF_MIB_TOP_M0B0SDR0_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x100) // D100
#define BN0_WF_MIB_TOP_M0B0SDR1_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x104) // D104
#define BN0_WF_MIB_TOP_M0B0SDR2_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x108) // D108
#define BN0_WF_MIB_TOP_M0B0SDR3_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x10C) // D10C
#define BN0_WF_MIB_TOP_M0B1SDR0_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x110) // D110
#define BN0_WF_MIB_TOP_M0B1SDR1_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x114) // D114
#define BN0_WF_MIB_TOP_M0B1SDR2_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x118) // D118
#define BN0_WF_MIB_TOP_M0B1SDR3_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x11C) // D11C
#define BN0_WF_MIB_TOP_M0B2SDR0_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x120) // D120
#define BN0_WF_MIB_TOP_M0B2SDR1_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x124) // D124
#define BN0_WF_MIB_TOP_M0B2SDR2_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x128) // D128
#define BN0_WF_MIB_TOP_M0B2SDR3_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x12C) // D12C
#define BN0_WF_MIB_TOP_M0B3SDR0_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x130) // D130
#define BN0_WF_MIB_TOP_M0B3SDR1_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x134) // D134
#define BN0_WF_MIB_TOP_M0B3SDR2_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x138) // D138
#define BN0_WF_MIB_TOP_M0B3SDR3_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x13C) // D13C
#define BN0_WF_MIB_TOP_M0DR12_ADDR                             (BN0_WF_MIB_TOP_BASE + 0x160) // D160
#define BN0_WF_MIB_TOP_M0DR13_ADDR                             (BN0_WF_MIB_TOP_BASE + 0x164) // D164
#define BN0_WF_MIB_TOP_M0DR14_ADDR                             (BN0_WF_MIB_TOP_BASE + 0x168) // D168
#define BN0_WF_MIB_TOP_M0DR15_ADDR                             (BN0_WF_MIB_TOP_BASE + 0x16C) // D16C
#define BN0_WF_MIB_TOP_M0DR16_ADDR                             (BN0_WF_MIB_TOP_BASE + 0x170) // D170
#define BN0_WF_MIB_TOP_M0DROPSR00_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x190) // D190
#define BN0_WF_MIB_TOP_M0DROPSR01_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x194) // D194
#define BN0_WF_MIB_TOP_M0SDR50_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x1DC) // D1DC
#define BN0_WF_MIB_TOP_M0SDR51_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x1E0) // D1E0
#define BN0_WF_MIB_TOP_MIB_RSVD_ADDR                           (BN0_WF_MIB_TOP_BASE + 0x3FC) // D3FC
#define BN0_WF_MIB_TOP_M0NSS1MCS0_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x400) // D400
#define BN0_WF_MIB_TOP_M0NSS1MCS1_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x404) // D404
#define BN0_WF_MIB_TOP_M0NSS1MCS2_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x408) // D408
#define BN0_WF_MIB_TOP_M0NSS1MCS3_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x40C) // D40C
#define BN0_WF_MIB_TOP_M0NSS1MCS4_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x410) // D410
#define BN0_WF_MIB_TOP_M0NSS1MCS5_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x414) // D414
#define BN0_WF_MIB_TOP_M0NSS1MCS6_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x418) // D418
#define BN0_WF_MIB_TOP_M0NSS1MCS7_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x41C) // D41C
#define BN0_WF_MIB_TOP_M0NSS1MCS8_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x420) // D420
#define BN0_WF_MIB_TOP_M0NSS1MCS9_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x424) // D424
#define BN0_WF_MIB_TOP_M0NSS2MCS0_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x428) // D428
#define BN0_WF_MIB_TOP_M0NSS2MCS1_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x42c) // D42C
#define BN0_WF_MIB_TOP_M0NSS2MCS2_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x430) // D430
#define BN0_WF_MIB_TOP_M0NSS2MCS3_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x434) // D434
#define BN0_WF_MIB_TOP_M0NSS2MCS4_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x438) // D438
#define BN0_WF_MIB_TOP_M0NSS2MCS5_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x43c) // D43C
#define BN0_WF_MIB_TOP_M0NSS2MCS6_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x440) // D440
#define BN0_WF_MIB_TOP_M0NSS2MCS7_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x444) // D444
#define BN0_WF_MIB_TOP_M0NSS2MCS8_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x448) // D448
#define BN0_WF_MIB_TOP_M0NSS2MCS9_ADDR                         (BN0_WF_MIB_TOP_BASE + 0x44c) // D44C
#define BN0_WF_MIB_TOP_M0TABT0_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x4A0) // D4A0
#define BN0_WF_MIB_TOP_M0TABT1_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x4A4) // D4A4
#define BN0_WF_MIB_TOP_M0TABT2_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x4A8) // D4A8
#define BN0_WF_MIB_TOP_M0TABT3_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x4AC) // D4AC
#define BN0_WF_MIB_TOP_M0CABT0_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x4B0) // D4B0
#define BN0_WF_MIB_TOP_M0CABT1_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x4B4) // D4B4
#define BN0_WF_MIB_TOP_M0ARNG0_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x4B8) // D4B8
#define BN0_WF_MIB_TOP_M0ARNG1_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x4BC) // D4BC
#define BN0_WF_MIB_TOP_M0ARNG2_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x4C0) // D4C0
#define BN0_WF_MIB_TOP_M0ARNG3_ADDR                            (BN0_WF_MIB_TOP_BASE + 0x4C4) // D4C4




/* =====================================================================================

  ---M0SCR0 (0x820ED000 + 0x00)---

    RX_FCS_ERROR_COUNT_EN[0]     - (RW) Enable RX FCS error count
    RX_FIFO_FULL_COUNT_EN[1]     - (RW) Enable RX FIFO full count
    RX_MPDU_COUNT_EN[2]          - (RW) Enable RX MPDU count
    CHANNEL_IDLE_COUNT_EN[3]     - (RW) Enable Channel idle count
    VEC_DROP_COUNT_EN[4]         - (RW) Enable Vector drop count
    DELIMITER_FAIL_COUNT_EN[5]   - (RW) Enable delimiter fail count
    VEC_MISMATCH_EN[6]           - (RW) Enable Vector mismatch count
    MDRDY_EVENT_EN[7]            - (RW) Enable MDRDY count
    RESERVED[8]                  - (RW) RESERVED
    RX_LEN_MISMATCH_EN[9]        - (RW) Enable RX length mismatch count
    AMDPU_RX_COUNT_EN[10]        - (RW) Enable AMPDU RX count
    PSCCA_TIME_EN[13..11]        - (RW) Enable PSCCA time count
    CCA_NAV_TX_TIME_EN[16..14]   - (RW) Enable CCA NAV TX time count
    BEACONTXCOUNT_EN[17]         - (RW) Enable beacon TX count
    ARB_TX_RWP_NEED_COUNT_EN[18] - (RW) Enable ARB TX enaming windows protected need count
    ARB_TX_RWP_FAIL_COUNT_EN[19] - (RW) Enable ARB TX enaming windows protected fail count
    TX_BW_CNT_EN[20]             - (RW) Enable the TX bandwidth counts
    TRX_AGG_RANGE_CNT_EN[21]     - (RW) Enable the TX aggregation range counts
    AMDPU_TX_COUNT_EN[22]        - (RW) Enable AMPDU TX count
    PHY_MIB_COUNT0_EN[23]        - (RW) Enable PHY MIB count 0
    RESERVED24[24]               - (RO) Reserved bits
    OFDM_CCK_MDRDY_TIME_EN[27..25] - (RW) Enable OFDM CCK MDRDY time count
    PED_TIME_EN[30..28]          - (RW) Enable Primary ED time count
    MIB_COUNTER_RD_CONTROL[31]   - (RW) Control the read clear function for all MIB counters, including.

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SCR0_MIB_COUNTER_RD_CONTROL_ADDR      BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_MIB_COUNTER_RD_CONTROL_MASK      0x80000000                // MIB_COUNTER_RD_CONTROL[31]
#define BN0_WF_MIB_TOP_M0SCR0_MIB_COUNTER_RD_CONTROL_SHFT      31
#define BN0_WF_MIB_TOP_M0SCR0_PED_TIME_EN_ADDR                 BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_PED_TIME_EN_MASK                 0x70000000                // PED_TIME_EN[30..28]
#define BN0_WF_MIB_TOP_M0SCR0_PED_TIME_EN_SHFT                 28
#define BN0_WF_MIB_TOP_M0SCR0_OFDM_CCK_MDRDY_TIME_EN_ADDR      BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_OFDM_CCK_MDRDY_TIME_EN_MASK      0x0E000000                // OFDM_CCK_MDRDY_TIME_EN[27..25]
#define BN0_WF_MIB_TOP_M0SCR0_OFDM_CCK_MDRDY_TIME_EN_SHFT      25
#define BN0_WF_MIB_TOP_M0SCR0_PHY_MIB_COUNT0_EN_ADDR           BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_PHY_MIB_COUNT0_EN_MASK           0x00800000                // PHY_MIB_COUNT0_EN[23]
#define BN0_WF_MIB_TOP_M0SCR0_PHY_MIB_COUNT0_EN_SHFT           23
#define BN0_WF_MIB_TOP_M0SCR0_AMDPU_TX_COUNT_EN_ADDR           BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_AMDPU_TX_COUNT_EN_MASK           0x00400000                // AMDPU_TX_COUNT_EN[22]
#define BN0_WF_MIB_TOP_M0SCR0_AMDPU_TX_COUNT_EN_SHFT           22
#define BN0_WF_MIB_TOP_M0SCR0_TRX_AGG_RANGE_CNT_EN_ADDR        BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_TRX_AGG_RANGE_CNT_EN_MASK        0x00200000                // TRX_AGG_RANGE_CNT_EN[21]
#define BN0_WF_MIB_TOP_M0SCR0_TRX_AGG_RANGE_CNT_EN_SHFT        21
#define BN0_WF_MIB_TOP_M0SCR0_TX_BW_CNT_EN_ADDR                BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_TX_BW_CNT_EN_MASK                0x00100000                // TX_BW_CNT_EN[20]
#define BN0_WF_MIB_TOP_M0SCR0_TX_BW_CNT_EN_SHFT                20
#define BN0_WF_MIB_TOP_M0SCR0_ARB_TX_RWP_FAIL_COUNT_EN_ADDR    BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_ARB_TX_RWP_FAIL_COUNT_EN_MASK    0x00080000                // ARB_TX_RWP_FAIL_COUNT_EN[19]
#define BN0_WF_MIB_TOP_M0SCR0_ARB_TX_RWP_FAIL_COUNT_EN_SHFT    19
#define BN0_WF_MIB_TOP_M0SCR0_ARB_TX_RWP_NEED_COUNT_EN_ADDR    BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_ARB_TX_RWP_NEED_COUNT_EN_MASK    0x00040000                // ARB_TX_RWP_NEED_COUNT_EN[18]
#define BN0_WF_MIB_TOP_M0SCR0_ARB_TX_RWP_NEED_COUNT_EN_SHFT    18
#define BN0_WF_MIB_TOP_M0SCR0_BEACONTXCOUNT_EN_ADDR            BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_BEACONTXCOUNT_EN_MASK            0x00020000                // BEACONTXCOUNT_EN[17]
#define BN0_WF_MIB_TOP_M0SCR0_BEACONTXCOUNT_EN_SHFT            17
#define BN0_WF_MIB_TOP_M0SCR0_CCA_NAV_TX_TIME_EN_ADDR          BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_CCA_NAV_TX_TIME_EN_MASK          0x0001C000                // CCA_NAV_TX_TIME_EN[16..14]
#define BN0_WF_MIB_TOP_M0SCR0_CCA_NAV_TX_TIME_EN_SHFT          14
#define BN0_WF_MIB_TOP_M0SCR0_PSCCA_TIME_EN_ADDR               BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_PSCCA_TIME_EN_MASK               0x00003800                // PSCCA_TIME_EN[13..11]
#define BN0_WF_MIB_TOP_M0SCR0_PSCCA_TIME_EN_SHFT               11
#define BN0_WF_MIB_TOP_M0SCR0_AMDPU_RX_COUNT_EN_ADDR           BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_AMDPU_RX_COUNT_EN_MASK           0x00000400                // AMDPU_RX_COUNT_EN[10]
#define BN0_WF_MIB_TOP_M0SCR0_AMDPU_RX_COUNT_EN_SHFT           10
#define BN0_WF_MIB_TOP_M0SCR0_RX_LEN_MISMATCH_EN_ADDR          BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_RX_LEN_MISMATCH_EN_MASK          0x00000200                // RX_LEN_MISMATCH_EN[9]
#define BN0_WF_MIB_TOP_M0SCR0_RX_LEN_MISMATCH_EN_SHFT          9
#define BN0_WF_MIB_TOP_M0SCR0_MDRDY_EVENT_EN_ADDR              BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_MDRDY_EVENT_EN_MASK              0x00000080                // MDRDY_EVENT_EN[7]
#define BN0_WF_MIB_TOP_M0SCR0_MDRDY_EVENT_EN_SHFT              7
#define BN0_WF_MIB_TOP_M0SCR0_VEC_MISMATCH_EN_ADDR             BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_VEC_MISMATCH_EN_MASK             0x00000040                // VEC_MISMATCH_EN[6]
#define BN0_WF_MIB_TOP_M0SCR0_VEC_MISMATCH_EN_SHFT             6
#define BN0_WF_MIB_TOP_M0SCR0_DELIMITER_FAIL_COUNT_EN_ADDR     BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_DELIMITER_FAIL_COUNT_EN_MASK     0x00000020                // DELIMITER_FAIL_COUNT_EN[5]
#define BN0_WF_MIB_TOP_M0SCR0_DELIMITER_FAIL_COUNT_EN_SHFT     5
#define BN0_WF_MIB_TOP_M0SCR0_VEC_DROP_COUNT_EN_ADDR           BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_VEC_DROP_COUNT_EN_MASK           0x00000010                // VEC_DROP_COUNT_EN[4]
#define BN0_WF_MIB_TOP_M0SCR0_VEC_DROP_COUNT_EN_SHFT           4
#define BN0_WF_MIB_TOP_M0SCR0_CHANNEL_IDLE_COUNT_EN_ADDR       BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_CHANNEL_IDLE_COUNT_EN_MASK       0x00000008                // CHANNEL_IDLE_COUNT_EN[3]
#define BN0_WF_MIB_TOP_M0SCR0_CHANNEL_IDLE_COUNT_EN_SHFT       3
#define BN0_WF_MIB_TOP_M0SCR0_RX_MPDU_COUNT_EN_ADDR            BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_RX_MPDU_COUNT_EN_MASK            0x00000004                // RX_MPDU_COUNT_EN[2]
#define BN0_WF_MIB_TOP_M0SCR0_RX_MPDU_COUNT_EN_SHFT            2
#define BN0_WF_MIB_TOP_M0SCR0_RX_FIFO_FULL_COUNT_EN_ADDR       BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_RX_FIFO_FULL_COUNT_EN_MASK       0x00000002                // RX_FIFO_FULL_COUNT_EN[1]
#define BN0_WF_MIB_TOP_M0SCR0_RX_FIFO_FULL_COUNT_EN_SHFT       1
#define BN0_WF_MIB_TOP_M0SCR0_RX_FCS_ERROR_COUNT_EN_ADDR       BN0_WF_MIB_TOP_M0SCR0_ADDR
#define BN0_WF_MIB_TOP_M0SCR0_RX_FCS_ERROR_COUNT_EN_MASK       0x00000001                // RX_FCS_ERROR_COUNT_EN[0]
#define BN0_WF_MIB_TOP_M0SCR0_RX_FCS_ERROR_COUNT_EN_SHFT       0

/* =====================================================================================

  ---M0PBSCR (0x820ED000 + 0x04)---

    RTSTXCOUNT0_EN[0]            - (RW) Enable RTS TX count for BSSID0
    RTSRETRYCOUNT0_EN[1]         - (RW) Enable RTS retry count for BSSID0
    BAMISSCOUNT0_EN[2]           - (RW) Enable BA miss count for BSSID0
    ACKFAILCOUNT0_EN[3]          - (RW) Enable ACK fail count for BSSID0
    FRAMERETRYCOUNT0_EN[4]       - (RW) Enable frame retry count for BSSID0
    FRAMERETRY2COUNT0_EN[5]      - (RW) Enable frame retry more than 2 count for BSSID0
    FRAMERETRY3COUNT0_EN[6]      - (RW) Enable frame retry more than 3 count for BSSID0
    RESERVED7[7]                 - (RO) Reserved bits
    RTSTXCOUNT1_EN[8]            - (RW) Enable RTS TX count for BSSID1
    RTSRETRYCOUNT1_EN[9]         - (RW) Enable RTS retry count for BSSID1
    BAMISSCOUNT1_EN[10]          - (RW) Enable BA miss count for BSSID1
    ACKFAILCOUNT1_EN[11]         - (RW) Enable ACK fail count for BSSID1
    FRAMERETRYCOUNT1_EN[12]      - (RW) Enable frame retry count for BSSID1
    FRAMERETRY2COUNT1_EN[13]     - (RW) Enable frame retry more than 2 count for BSSID1
    FRAMERETRY3COUNT1_EN[14]     - (RW) Enable frame retry more than 3 count for BSSID1
    RESERVED15[15]               - (RO) Reserved bits
    RTSTXCOUNT2_EN[16]           - (RW) Enable RTS TX count for BSSID2
    RTSRETRYCOUNT2_EN[17]        - (RW) Enable RTS retry count for BSSID2
    BAMISSCOUNT2_EN[18]          - (RW) Enable BA miss count for BSSID2
    ACKFAILCOUNT2_EN[19]         - (RW) Enable ACK fail count for BSSID2
    FRAMERETRYCOUNT2_EN[20]      - (RW) Enable frame retry count for BSSID2
    FRAMERETRY2COUNT2_EN[21]     - (RW) Enable frame retry more than 2 count for BSSID2
    FRAMERETRY3COUNT2_EN[22]     - (RW) Enable frame retry more than 3 count for BSSID2
    RESERVED23[23]               - (RO) Reserved bits
    RTSTXCOUNT3_EN[24]           - (RW) Enable RTS TX count for BSSID3
    RTSRETRYCOUNT3_EN[25]        - (RW) Enable RTS retry count for BSSID3
    BAMISSCOUNT3_EN[26]          - (RW) Enable BA miss count for BSSID3
    ACKFAILCOUNT3_EN[27]         - (RW) Enable ACK fail count for BSSID3
    FRAMERETRYCOUNT3_EN[28]      - (RW) Enable frame retry count for BSSID3
    FRAMERETRY2COUNT3_EN[29]     - (RW) Enable frame retry more than 2 count for BSSID3
    FRAMERETRY3COUNT3_EN[30]     - (RW) Enable frame retry more than 3 count for BSSID3
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY3COUNT3_EN_ADDR       BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY3COUNT3_EN_MASK       0x40000000                // FRAMERETRY3COUNT3_EN[30]
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY3COUNT3_EN_SHFT       30
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY2COUNT3_EN_ADDR       BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY2COUNT3_EN_MASK       0x20000000                // FRAMERETRY2COUNT3_EN[29]
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY2COUNT3_EN_SHFT       29
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRYCOUNT3_EN_ADDR        BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRYCOUNT3_EN_MASK        0x10000000                // FRAMERETRYCOUNT3_EN[28]
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRYCOUNT3_EN_SHFT        28
#define BN0_WF_MIB_TOP_M0PBSCR_ACKFAILCOUNT3_EN_ADDR           BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_ACKFAILCOUNT3_EN_MASK           0x08000000                // ACKFAILCOUNT3_EN[27]
#define BN0_WF_MIB_TOP_M0PBSCR_ACKFAILCOUNT3_EN_SHFT           27
#define BN0_WF_MIB_TOP_M0PBSCR_BAMISSCOUNT3_EN_ADDR            BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_BAMISSCOUNT3_EN_MASK            0x04000000                // BAMISSCOUNT3_EN[26]
#define BN0_WF_MIB_TOP_M0PBSCR_BAMISSCOUNT3_EN_SHFT            26
#define BN0_WF_MIB_TOP_M0PBSCR_RTSRETRYCOUNT3_EN_ADDR          BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_RTSRETRYCOUNT3_EN_MASK          0x02000000                // RTSRETRYCOUNT3_EN[25]
#define BN0_WF_MIB_TOP_M0PBSCR_RTSRETRYCOUNT3_EN_SHFT          25
#define BN0_WF_MIB_TOP_M0PBSCR_RTSTXCOUNT3_EN_ADDR             BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_RTSTXCOUNT3_EN_MASK             0x01000000                // RTSTXCOUNT3_EN[24]
#define BN0_WF_MIB_TOP_M0PBSCR_RTSTXCOUNT3_EN_SHFT             24
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY3COUNT2_EN_ADDR       BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY3COUNT2_EN_MASK       0x00400000                // FRAMERETRY3COUNT2_EN[22]
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY3COUNT2_EN_SHFT       22
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY2COUNT2_EN_ADDR       BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY2COUNT2_EN_MASK       0x00200000                // FRAMERETRY2COUNT2_EN[21]
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY2COUNT2_EN_SHFT       21
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRYCOUNT2_EN_ADDR        BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRYCOUNT2_EN_MASK        0x00100000                // FRAMERETRYCOUNT2_EN[20]
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRYCOUNT2_EN_SHFT        20
#define BN0_WF_MIB_TOP_M0PBSCR_ACKFAILCOUNT2_EN_ADDR           BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_ACKFAILCOUNT2_EN_MASK           0x00080000                // ACKFAILCOUNT2_EN[19]
#define BN0_WF_MIB_TOP_M0PBSCR_ACKFAILCOUNT2_EN_SHFT           19
#define BN0_WF_MIB_TOP_M0PBSCR_BAMISSCOUNT2_EN_ADDR            BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_BAMISSCOUNT2_EN_MASK            0x00040000                // BAMISSCOUNT2_EN[18]
#define BN0_WF_MIB_TOP_M0PBSCR_BAMISSCOUNT2_EN_SHFT            18
#define BN0_WF_MIB_TOP_M0PBSCR_RTSRETRYCOUNT2_EN_ADDR          BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_RTSRETRYCOUNT2_EN_MASK          0x00020000                // RTSRETRYCOUNT2_EN[17]
#define BN0_WF_MIB_TOP_M0PBSCR_RTSRETRYCOUNT2_EN_SHFT          17
#define BN0_WF_MIB_TOP_M0PBSCR_RTSTXCOUNT2_EN_ADDR             BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_RTSTXCOUNT2_EN_MASK             0x00010000                // RTSTXCOUNT2_EN[16]
#define BN0_WF_MIB_TOP_M0PBSCR_RTSTXCOUNT2_EN_SHFT             16
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY3COUNT1_EN_ADDR       BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY3COUNT1_EN_MASK       0x00004000                // FRAMERETRY3COUNT1_EN[14]
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY3COUNT1_EN_SHFT       14
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY2COUNT1_EN_ADDR       BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY2COUNT1_EN_MASK       0x00002000                // FRAMERETRY2COUNT1_EN[13]
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY2COUNT1_EN_SHFT       13
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRYCOUNT1_EN_ADDR        BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRYCOUNT1_EN_MASK        0x00001000                // FRAMERETRYCOUNT1_EN[12]
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRYCOUNT1_EN_SHFT        12
#define BN0_WF_MIB_TOP_M0PBSCR_ACKFAILCOUNT1_EN_ADDR           BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_ACKFAILCOUNT1_EN_MASK           0x00000800                // ACKFAILCOUNT1_EN[11]
#define BN0_WF_MIB_TOP_M0PBSCR_ACKFAILCOUNT1_EN_SHFT           11
#define BN0_WF_MIB_TOP_M0PBSCR_BAMISSCOUNT1_EN_ADDR            BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_BAMISSCOUNT1_EN_MASK            0x00000400                // BAMISSCOUNT1_EN[10]
#define BN0_WF_MIB_TOP_M0PBSCR_BAMISSCOUNT1_EN_SHFT            10
#define BN0_WF_MIB_TOP_M0PBSCR_RTSRETRYCOUNT1_EN_ADDR          BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_RTSRETRYCOUNT1_EN_MASK          0x00000200                // RTSRETRYCOUNT1_EN[9]
#define BN0_WF_MIB_TOP_M0PBSCR_RTSRETRYCOUNT1_EN_SHFT          9
#define BN0_WF_MIB_TOP_M0PBSCR_RTSTXCOUNT1_EN_ADDR             BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_RTSTXCOUNT1_EN_MASK             0x00000100                // RTSTXCOUNT1_EN[8]
#define BN0_WF_MIB_TOP_M0PBSCR_RTSTXCOUNT1_EN_SHFT             8
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY3COUNT0_EN_ADDR       BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY3COUNT0_EN_MASK       0x00000040                // FRAMERETRY3COUNT0_EN[6]
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY3COUNT0_EN_SHFT       6
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY2COUNT0_EN_ADDR       BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY2COUNT0_EN_MASK       0x00000020                // FRAMERETRY2COUNT0_EN[5]
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRY2COUNT0_EN_SHFT       5
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRYCOUNT0_EN_ADDR        BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRYCOUNT0_EN_MASK        0x00000010                // FRAMERETRYCOUNT0_EN[4]
#define BN0_WF_MIB_TOP_M0PBSCR_FRAMERETRYCOUNT0_EN_SHFT        4
#define BN0_WF_MIB_TOP_M0PBSCR_ACKFAILCOUNT0_EN_ADDR           BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_ACKFAILCOUNT0_EN_MASK           0x00000008                // ACKFAILCOUNT0_EN[3]
#define BN0_WF_MIB_TOP_M0PBSCR_ACKFAILCOUNT0_EN_SHFT           3
#define BN0_WF_MIB_TOP_M0PBSCR_BAMISSCOUNT0_EN_ADDR            BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_BAMISSCOUNT0_EN_MASK            0x00000004                // BAMISSCOUNT0_EN[2]
#define BN0_WF_MIB_TOP_M0PBSCR_BAMISSCOUNT0_EN_SHFT            2
#define BN0_WF_MIB_TOP_M0PBSCR_RTSRETRYCOUNT0_EN_ADDR          BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_RTSRETRYCOUNT0_EN_MASK          0x00000002                // RTSRETRYCOUNT0_EN[1]
#define BN0_WF_MIB_TOP_M0PBSCR_RTSRETRYCOUNT0_EN_SHFT          1
#define BN0_WF_MIB_TOP_M0PBSCR_RTSTXCOUNT0_EN_ADDR             BN0_WF_MIB_TOP_M0PBSCR_ADDR
#define BN0_WF_MIB_TOP_M0PBSCR_RTSTXCOUNT0_EN_MASK             0x00000001                // RTSTXCOUNT0_EN[0]
#define BN0_WF_MIB_TOP_M0PBSCR_RTSTXCOUNT0_EN_SHFT             0

/* =====================================================================================

  ---M0SCR1 (0x820ED000 + 0x08)---

    AP_BGND_SCAN_EN[0]           - (RW) Enable AP background scan
    EBFTXINC_EN[1]               - (RW) Enable EBF TX count
    IBFTXINC_EN[2]               - (RW) Enable IBF TX count
    MUBFTXINC_EN[3]              - (RW) Enable MUBF TX count
    MAC2PHY_TX_TIME_EN[4]        - (RW) Enable MAC2PHY tx time count
    DDLMT_TX_EN[5]               - (RW) Enable Dummy Delimiter Range counts
    MU_TXCNT_EN[6]               - (RW) Enable MU TX count
    SU_TXCNT_EN[7]               - (RW) Enable SU TX count
    TXDUR_EN[8]                  - (RW) Enable TXDUR count
    RXDUR_EN[9]                  - (RW) Enable RXDUR count
    TXCTRL_EN[10]                - (RW) Enable control frame tx counter for band0
    MGMT_FRAMERETRY_CNT_EN[11]   - (RW) Enable management frame retry counter for band0
    DATA_FRAMERETRY_CNT_EN[12]   - (RW) Enable data frame retry counter for band0
    RX_OUT_OF_RANGE_COUNT_EN[13] - (RW) Enable counting RX_OUT_OF_RANGE_COUNT
    RESERVED14[15..14]           - (RO) Reserved bits
    NON_ED_EN[16]                - (RW) Enable NON_ED for P_ED_TIME
    RX_NON_NO_DATA_CNT_EN[17]    - (RW) Enable RX non-no-data counter
    RX_PARTIAL_BCN_CNT_EN[18]    - (RW) Enable RX partoal beacon counter
    MOZART_ED_TRIG_CNT_EN[19]    - (RW) Enable Energy detection trigger counter
    TX_TIME_CNT_EN[20]           - (RW) Enable transmission time counter
    OPPO_PS_RX_DIS_CNT_EN[21]    - (RW) Enable oppo power save counter
    OPPO_PS_RX_DIS_TIME_CNT_EN[22] - (RW) Enable oppo power save time counter
    OPPO_SX_OFF_CNT_EN[23]       - (RW) Enable SX power off counter
    DTIM_UPDATE_CHK_FAIL_CNT_EN[24] - (RW) Enable dtim update check fail counter
    DBNSS_CNT_EN[25]             - (RW) Enable DBNSS counter
    RX_FCS_OK_CNT_EN[26]         - (RW) Enable RX FCS OK counter
    RESERVED27[31..27]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SCR1_RX_FCS_OK_CNT_EN_ADDR            BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_RX_FCS_OK_CNT_EN_MASK            0x04000000                // RX_FCS_OK_CNT_EN[26]
#define BN0_WF_MIB_TOP_M0SCR1_RX_FCS_OK_CNT_EN_SHFT            26
#define BN0_WF_MIB_TOP_M0SCR1_DBNSS_CNT_EN_ADDR                BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_DBNSS_CNT_EN_MASK                0x02000000                // DBNSS_CNT_EN[25]
#define BN0_WF_MIB_TOP_M0SCR1_DBNSS_CNT_EN_SHFT                25
#define BN0_WF_MIB_TOP_M0SCR1_DTIM_UPDATE_CHK_FAIL_CNT_EN_ADDR BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_DTIM_UPDATE_CHK_FAIL_CNT_EN_MASK 0x01000000                // DTIM_UPDATE_CHK_FAIL_CNT_EN[24]
#define BN0_WF_MIB_TOP_M0SCR1_DTIM_UPDATE_CHK_FAIL_CNT_EN_SHFT 24
#define BN0_WF_MIB_TOP_M0SCR1_OPPO_SX_OFF_CNT_EN_ADDR          BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_OPPO_SX_OFF_CNT_EN_MASK          0x00800000                // OPPO_SX_OFF_CNT_EN[23]
#define BN0_WF_MIB_TOP_M0SCR1_OPPO_SX_OFF_CNT_EN_SHFT          23
#define BN0_WF_MIB_TOP_M0SCR1_OPPO_PS_RX_DIS_TIME_CNT_EN_ADDR  BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_OPPO_PS_RX_DIS_TIME_CNT_EN_MASK  0x00400000                // OPPO_PS_RX_DIS_TIME_CNT_EN[22]
#define BN0_WF_MIB_TOP_M0SCR1_OPPO_PS_RX_DIS_TIME_CNT_EN_SHFT  22
#define BN0_WF_MIB_TOP_M0SCR1_OPPO_PS_RX_DIS_CNT_EN_ADDR       BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_OPPO_PS_RX_DIS_CNT_EN_MASK       0x00200000                // OPPO_PS_RX_DIS_CNT_EN[21]
#define BN0_WF_MIB_TOP_M0SCR1_OPPO_PS_RX_DIS_CNT_EN_SHFT       21
#define BN0_WF_MIB_TOP_M0SCR1_TX_TIME_CNT_EN_ADDR              BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_TX_TIME_CNT_EN_MASK              0x00100000                // TX_TIME_CNT_EN[20]
#define BN0_WF_MIB_TOP_M0SCR1_TX_TIME_CNT_EN_SHFT              20
#define BN0_WF_MIB_TOP_M0SCR1_MOZART_ED_TRIG_CNT_EN_ADDR       BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_MOZART_ED_TRIG_CNT_EN_MASK       0x00080000                // MOZART_ED_TRIG_CNT_EN[19]
#define BN0_WF_MIB_TOP_M0SCR1_MOZART_ED_TRIG_CNT_EN_SHFT       19
#define BN0_WF_MIB_TOP_M0SCR1_RX_PARTIAL_BCN_CNT_EN_ADDR       BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_RX_PARTIAL_BCN_CNT_EN_MASK       0x00040000                // RX_PARTIAL_BCN_CNT_EN[18]
#define BN0_WF_MIB_TOP_M0SCR1_RX_PARTIAL_BCN_CNT_EN_SHFT       18
#define BN0_WF_MIB_TOP_M0SCR1_RX_NON_NO_DATA_CNT_EN_ADDR       BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_RX_NON_NO_DATA_CNT_EN_MASK       0x00020000                // RX_NON_NO_DATA_CNT_EN[17]
#define BN0_WF_MIB_TOP_M0SCR1_RX_NON_NO_DATA_CNT_EN_SHFT       17
#define BN0_WF_MIB_TOP_M0SCR1_NON_ED_EN_ADDR                   BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_NON_ED_EN_MASK                   0x00010000                // NON_ED_EN[16]
#define BN0_WF_MIB_TOP_M0SCR1_NON_ED_EN_SHFT                   16
#define BN0_WF_MIB_TOP_M0SCR1_RX_OUT_OF_RANGE_COUNT_EN_ADDR    BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_RX_OUT_OF_RANGE_COUNT_EN_MASK    0x00002000                // RX_OUT_OF_RANGE_COUNT_EN[13]
#define BN0_WF_MIB_TOP_M0SCR1_RX_OUT_OF_RANGE_COUNT_EN_SHFT    13
#define BN0_WF_MIB_TOP_M0SCR1_DATA_FRAMERETRY_CNT_EN_ADDR      BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_DATA_FRAMERETRY_CNT_EN_MASK      0x00001000                // DATA_FRAMERETRY_CNT_EN[12]
#define BN0_WF_MIB_TOP_M0SCR1_DATA_FRAMERETRY_CNT_EN_SHFT      12
#define BN0_WF_MIB_TOP_M0SCR1_MGMT_FRAMERETRY_CNT_EN_ADDR      BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_MGMT_FRAMERETRY_CNT_EN_MASK      0x00000800                // MGMT_FRAMERETRY_CNT_EN[11]
#define BN0_WF_MIB_TOP_M0SCR1_MGMT_FRAMERETRY_CNT_EN_SHFT      11
#define BN0_WF_MIB_TOP_M0SCR1_TXCTRL_EN_ADDR                   BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_TXCTRL_EN_MASK                   0x00000400                // TXCTRL_EN[10]
#define BN0_WF_MIB_TOP_M0SCR1_TXCTRL_EN_SHFT                   10
#define BN0_WF_MIB_TOP_M0SCR1_RXDUR_EN_ADDR                    BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_RXDUR_EN_MASK                    0x00000200                // RXDUR_EN[9]
#define BN0_WF_MIB_TOP_M0SCR1_RXDUR_EN_SHFT                    9
#define BN0_WF_MIB_TOP_M0SCR1_TXDUR_EN_ADDR                    BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_TXDUR_EN_MASK                    0x00000100                // TXDUR_EN[8]
#define BN0_WF_MIB_TOP_M0SCR1_TXDUR_EN_SHFT                    8
#define BN0_WF_MIB_TOP_M0SCR1_SU_TXCNT_EN_ADDR                 BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_SU_TXCNT_EN_MASK                 0x00000080                // SU_TXCNT_EN[7]
#define BN0_WF_MIB_TOP_M0SCR1_SU_TXCNT_EN_SHFT                 7
#define BN0_WF_MIB_TOP_M0SCR1_MU_TXCNT_EN_ADDR                 BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_MU_TXCNT_EN_MASK                 0x00000040                // MU_TXCNT_EN[6]
#define BN0_WF_MIB_TOP_M0SCR1_MU_TXCNT_EN_SHFT                 6
#define BN0_WF_MIB_TOP_M0SCR1_DDLMT_TX_EN_ADDR                 BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_DDLMT_TX_EN_MASK                 0x00000020                // DDLMT_TX_EN[5]
#define BN0_WF_MIB_TOP_M0SCR1_DDLMT_TX_EN_SHFT                 5
#define BN0_WF_MIB_TOP_M0SCR1_MAC2PHY_TX_TIME_EN_ADDR          BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_MAC2PHY_TX_TIME_EN_MASK          0x00000010                // MAC2PHY_TX_TIME_EN[4]
#define BN0_WF_MIB_TOP_M0SCR1_MAC2PHY_TX_TIME_EN_SHFT          4
#define BN0_WF_MIB_TOP_M0SCR1_MUBFTXINC_EN_ADDR                BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_MUBFTXINC_EN_MASK                0x00000008                // MUBFTXINC_EN[3]
#define BN0_WF_MIB_TOP_M0SCR1_MUBFTXINC_EN_SHFT                3
#define BN0_WF_MIB_TOP_M0SCR1_IBFTXINC_EN_ADDR                 BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_IBFTXINC_EN_MASK                 0x00000004                // IBFTXINC_EN[2]
#define BN0_WF_MIB_TOP_M0SCR1_IBFTXINC_EN_SHFT                 2
#define BN0_WF_MIB_TOP_M0SCR1_EBFTXINC_EN_ADDR                 BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_EBFTXINC_EN_MASK                 0x00000002                // EBFTXINC_EN[1]
#define BN0_WF_MIB_TOP_M0SCR1_EBFTXINC_EN_SHFT                 1
#define BN0_WF_MIB_TOP_M0SCR1_AP_BGND_SCAN_EN_ADDR             BN0_WF_MIB_TOP_M0SCR1_ADDR
#define BN0_WF_MIB_TOP_M0SCR1_AP_BGND_SCAN_EN_MASK             0x00000001                // AP_BGND_SCAN_EN[0]
#define BN0_WF_MIB_TOP_M0SCR1_AP_BGND_SCAN_EN_SHFT             0

/* =====================================================================================

  ---M0MISCCR (0x820ED000 + 0x00c)---

    LTO_DROP_CLR_EN[0]           - (RW) enable ro disable clearing the counter when LTO_DROP_COUNT is read
    RTS_DROP_CLR_EN[1]           - (RW) enable ro disable clearing the counter when RTS_DROP_COUNT is read
    MPDU_RETRY_DROP_CLR_EN[2]    - (RW) enable ro disable clearing the counter when MPDU_RETRY_DROP_COUNT is read
    SEC_CCA_SEL[4..3]            - (RW) select Secondary CCA Sources: 20MHz, 40MHz or 80MHz
    TRX_ARNG_MODE[6..5]          - (RW) There are 8 AGG Range Counters that are shared between TX and RX Aggregation Counting. MIB supports 3 modes; 
                                       2'b00: 8-to-0 mode (RX AGG disabled)
                                       2'b01: 4-to-4 mode (TX AGG uses 4 counters and RX AGG uses 4 counters)
                                       2'b10: 0-to-8  mode (TX AGG disabled)
    RESERVED7[7]                 - (RO) Reserved bits
    LTO_DROP_INC_EN[8]           - (RW) enable or disable Life Time Out Counting
    RTS_DROP_INC_EN[9]           - (RW) enable or disable RTS Drop Counting
    MPDU_RETRY_DROP_INC_EN[10]   - (RW) enable or disable MPDU Retry Drop Counting
    RESERVED11[31..11]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0MISCCR_MPDU_RETRY_DROP_INC_EN_ADDR    BN0_WF_MIB_TOP_M0MISCCR_ADDR
#define BN0_WF_MIB_TOP_M0MISCCR_MPDU_RETRY_DROP_INC_EN_MASK    0x00000400                // MPDU_RETRY_DROP_INC_EN[10]
#define BN0_WF_MIB_TOP_M0MISCCR_MPDU_RETRY_DROP_INC_EN_SHFT    10
#define BN0_WF_MIB_TOP_M0MISCCR_RTS_DROP_INC_EN_ADDR           BN0_WF_MIB_TOP_M0MISCCR_ADDR
#define BN0_WF_MIB_TOP_M0MISCCR_RTS_DROP_INC_EN_MASK           0x00000200                // RTS_DROP_INC_EN[9]
#define BN0_WF_MIB_TOP_M0MISCCR_RTS_DROP_INC_EN_SHFT           9
#define BN0_WF_MIB_TOP_M0MISCCR_LTO_DROP_INC_EN_ADDR           BN0_WF_MIB_TOP_M0MISCCR_ADDR
#define BN0_WF_MIB_TOP_M0MISCCR_LTO_DROP_INC_EN_MASK           0x00000100                // LTO_DROP_INC_EN[8]
#define BN0_WF_MIB_TOP_M0MISCCR_LTO_DROP_INC_EN_SHFT           8
#define BN0_WF_MIB_TOP_M0MISCCR_TRX_ARNG_MODE_ADDR             BN0_WF_MIB_TOP_M0MISCCR_ADDR
#define BN0_WF_MIB_TOP_M0MISCCR_TRX_ARNG_MODE_MASK             0x00000060                // TRX_ARNG_MODE[6..5]
#define BN0_WF_MIB_TOP_M0MISCCR_TRX_ARNG_MODE_SHFT             5
#define BN0_WF_MIB_TOP_M0MISCCR_SEC_CCA_SEL_ADDR               BN0_WF_MIB_TOP_M0MISCCR_ADDR
#define BN0_WF_MIB_TOP_M0MISCCR_SEC_CCA_SEL_MASK               0x00000018                // SEC_CCA_SEL[4..3]
#define BN0_WF_MIB_TOP_M0MISCCR_SEC_CCA_SEL_SHFT               3
#define BN0_WF_MIB_TOP_M0MISCCR_MPDU_RETRY_DROP_CLR_EN_ADDR    BN0_WF_MIB_TOP_M0MISCCR_ADDR
#define BN0_WF_MIB_TOP_M0MISCCR_MPDU_RETRY_DROP_CLR_EN_MASK    0x00000004                // MPDU_RETRY_DROP_CLR_EN[2]
#define BN0_WF_MIB_TOP_M0MISCCR_MPDU_RETRY_DROP_CLR_EN_SHFT    2
#define BN0_WF_MIB_TOP_M0MISCCR_RTS_DROP_CLR_EN_ADDR           BN0_WF_MIB_TOP_M0MISCCR_ADDR
#define BN0_WF_MIB_TOP_M0MISCCR_RTS_DROP_CLR_EN_MASK           0x00000002                // RTS_DROP_CLR_EN[1]
#define BN0_WF_MIB_TOP_M0MISCCR_RTS_DROP_CLR_EN_SHFT           1
#define BN0_WF_MIB_TOP_M0MISCCR_LTO_DROP_CLR_EN_ADDR           BN0_WF_MIB_TOP_M0MISCCR_ADDR
#define BN0_WF_MIB_TOP_M0MISCCR_LTO_DROP_CLR_EN_MASK           0x00000001                // LTO_DROP_CLR_EN[0]
#define BN0_WF_MIB_TOP_M0MISCCR_LTO_DROP_CLR_EN_SHFT           0

/* =====================================================================================

  ---M0SDR0 (0x820ED000 + 0x10)---

    BEACONTXCOUNT[15..0]         - (RW) This counter shall be incremented for a beacon transmitted successfully.
                                     Enable when BEACONTXCOUNT_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_ADDR               BN0_WF_MIB_TOP_M0SDR0_ADDR
#define BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK               0x0000FFFF                // BEACONTXCOUNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_SHFT               0

/* =====================================================================================

  ---M0SDR3 (0x820ED000 + 0x14)---

    RX_FCS_ERROR_COUNT[15..0]    - (RW) This counter shall increment when an FCS error is detected in a received MPDU.
                                     Enable when RX_FCS_ERROR_COUNT_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR3_RX_FCS_ERROR_COUNT_ADDR          BN0_WF_MIB_TOP_M0SDR3_ADDR
#define BN0_WF_MIB_TOP_M0SDR3_RX_FCS_ERROR_COUNT_MASK          0x0000FFFF                // RX_FCS_ERROR_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR3_RX_FCS_ERROR_COUNT_SHFT          0

/* =====================================================================================

  ---M0SDR4 (0x820ED000 + 0x18)---

    RX_FIFO_FULL_COUNT[15..0]    - (RW) Counter of the number of the packets which pass RFCR but are dropped due to FIFO full.
                                     Enable when RX_FIFO_FULL_COUNT_EN = 1
    RX_OUT_OF_RANGE_COUNT[23..16] - (RW) 1. a MPDU passed RX filter and encounter its PPDU length > PPDU max threshold (RMAC.CR.MAXMIN_LEN) or
                                     2. a MPDU passed RX filter and encounter its PPDU length < PPDU min threshold (RMAC.CR.MAXMIN_LEN) and not a NDP
                                     3. a MPDU passed RX filter and encounter its MPDU length > MPDU max threshold (RMAC.CR.MISC)
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR4_RX_OUT_OF_RANGE_COUNT_ADDR       BN0_WF_MIB_TOP_M0SDR4_ADDR
#define BN0_WF_MIB_TOP_M0SDR4_RX_OUT_OF_RANGE_COUNT_MASK       0x00FF0000                // RX_OUT_OF_RANGE_COUNT[23..16]
#define BN0_WF_MIB_TOP_M0SDR4_RX_OUT_OF_RANGE_COUNT_SHFT       16
#define BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_ADDR          BN0_WF_MIB_TOP_M0SDR4_ADDR
#define BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK          0x0000FFFF                // RX_FIFO_FULL_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_SHFT          0

/* =====================================================================================

  ---M0SDR5 (0x820ED000 + 0x1C)---

    RX_MPDU_COUNT[31..0]         - (RW) This counter shall be incremented for each successfully received MPDU.
                                     Enable when RX_MPDU_COUNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_ADDR               BN0_WF_MIB_TOP_M0SDR5_ADDR
#define BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK               0xFFFFFFFF                // RX_MPDU_COUNT[31..0]
#define BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_SHFT               0

/* =====================================================================================

  ---M0SDR6 (0x820ED000 + 0x20)---

    CHANNEL_IDLE_COUNT[15..0]    - (RW) Channel idle count in unit of slot. The counter will be added 1 at every slot boundary if the channel is idle.
                                     Enable when CHANNEL_IDLE_COUNT_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_ADDR          BN0_WF_MIB_TOP_M0SDR6_ADDR
#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK          0x0000FFFF                // CHANNEL_IDLE_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_SHFT          0

/* =====================================================================================

  ---M0SDR7 (0x820ED000 + 0x24)---

    VEC_MISS_COUNT[15..0]        - (RW) This counter shall be incremented when Rx queue and vector queue mismatch.
                                     Enable when VEC_MISMATCH_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_ADDR              BN0_WF_MIB_TOP_M0SDR7_ADDR
#define BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK              0x0000FFFF                // VEC_MISS_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_SHFT              0

/* =====================================================================================

  ---M0SDR8 (0x820ED000 + 0x28)---

    DELIMITER_FAIL_COUNT[15..0]  - (RW) This counter shall be incremented when an A-MPDU delimiter has CRC error when this is the first CRC error in the received A-MPDU or when the previous delimiter has been decoded correctly.
                                     Enable when DELIMITER_FAIL_COUNT_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_ADDR        BN0_WF_MIB_TOP_M0SDR8_ADDR
#define BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK        0x0000FFFF                // DELIMITER_FAIL_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_SHFT        0

/* =====================================================================================

  ---M0SDR9 (0x820ED000 + 0x2C)---

    CCA_NAV_TX_TIME[23..0]       - (RW) NAV, CCA, or TX active timer in unit of TU, used for Measurement. (channel busy time)
                                     Enable when CCA_NAV_TX_TIME_EN = 1
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_ADDR             BN0_WF_MIB_TOP_M0SDR9_ADDR
#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK             0x00FFFFFF                // CCA_NAV_TX_TIME[23..0]
#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_SHFT             0

/* =====================================================================================

  ---M0SDR10 (0x820ED000 + 0x30)---

    RX_MDRDY_COUNT[25..0]        - (RW) This counter shall be incremented for each MDRDY rising edge occurs.
                                     Enable when MDRDY_EVENT_EN = 1
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR10_RX_MDRDY_COUNT_ADDR             BN0_WF_MIB_TOP_M0SDR10_ADDR
#define BN0_WF_MIB_TOP_M0SDR10_RX_MDRDY_COUNT_MASK             0x03FFFFFF                // RX_MDRDY_COUNT[25..0]
#define BN0_WF_MIB_TOP_M0SDR10_RX_MDRDY_COUNT_SHFT             0

/* =====================================================================================

  ---M0SDR11 (0x820ED000 + 0x34)---

    RX_LEN_MISMATCH[15..0]       - (RW) This counter shall be incremented when PHY/MAC RX length mismatch condition occurs
                                     Enable when RX_LEN_MISMATCH_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_ADDR            BN0_WF_MIB_TOP_M0SDR11_ADDR
#define BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK            0x0000FFFF                // RX_LEN_MISMATCH[15..0]
#define BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_SHFT            0

/* =====================================================================================

  ---M0SDR12 (0x820ED000 + 0x38)---

    AMPDU_COUNT[31..0]           - (RW) This counter shall be incremented when Tx APMDU occurs
                                     Enable when AMPDU_TX_COUNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR12_AMPDU_COUNT_ADDR                BN0_WF_MIB_TOP_M0SDR12_ADDR
#define BN0_WF_MIB_TOP_M0SDR12_AMPDU_COUNT_MASK                0xFFFFFFFF                // AMPDU_COUNT[31..0]
#define BN0_WF_MIB_TOP_M0SDR12_AMPDU_COUNT_SHFT                0

/* =====================================================================================

  ---M0SDR13 (0x820ED000 + 0x3C)---

    AMPDU_EARLYSTOP_COUNT[15..0] - (RW) This counter shall be incremented when AMPDU is stopped by Queue Empdy occurs
                                     Enable when AMPDU_TX_COUNT_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR13_AMPDU_EARLYSTOP_COUNT_ADDR      BN0_WF_MIB_TOP_M0SDR13_ADDR
#define BN0_WF_MIB_TOP_M0SDR13_AMPDU_EARLYSTOP_COUNT_MASK      0x0000FFFF                // AMPDU_EARLYSTOP_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR13_AMPDU_EARLYSTOP_COUNT_SHFT      0

/* =====================================================================================

  ---M0SDR14 (0x820ED000 + 0x40)---

    AMPDU_MPDU_COUNT[23..0]      - (RW) This counter shall count all MPDUs whether success or not in AMPDU
                                     Enable when AMPDU_TX_COUNT_EN = 1
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR14_AMPDU_MPDU_COUNT_ADDR           BN0_WF_MIB_TOP_M0SDR14_ADDR
#define BN0_WF_MIB_TOP_M0SDR14_AMPDU_MPDU_COUNT_MASK           0x00FFFFFF                // AMPDU_MPDU_COUNT[23..0]
#define BN0_WF_MIB_TOP_M0SDR14_AMPDU_MPDU_COUNT_SHFT           0

/* =====================================================================================

  ---M0SDR15 (0x820ED000 + 0x44)---

    AMPDU_ACKED_COUNT[23..0]     - (RW) This counter shall count all MPDUs which are success in AMPDU
                                     Enable when AMPDU_TX_COUNT_EN = 1
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR15_AMPDU_ACKED_COUNT_ADDR          BN0_WF_MIB_TOP_M0SDR15_ADDR
#define BN0_WF_MIB_TOP_M0SDR15_AMPDU_ACKED_COUNT_MASK          0x00FFFFFF                // AMPDU_ACKED_COUNT[23..0]
#define BN0_WF_MIB_TOP_M0SDR15_AMPDU_ACKED_COUNT_SHFT          0

/* =====================================================================================

  ---M0SDR16 (0x820ED000 + 0x48)---

    P_CCA_TIME[23..0]            - (RW) Primary CCA active counter is in unit of us. This counter is started on rising edge of primary CCA and stopped on falling edge of primary CCA, used for Measurement. Primary CCA is from (MDRDY|pED). (primary channel busy time) The counter is saturated mode.
                                     Enable when PSCCA_TIME_EN = 1
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_ADDR                 BN0_WF_MIB_TOP_M0SDR16_ADDR
#define BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK                 0x00FFFFFF                // P_CCA_TIME[23..0]
#define BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_SHFT                 0

/* =====================================================================================

  ---M0SDR17 (0x820ED000 + 0x4C)---

    S_CCA_TIME[23..0]            - (RW) Secondary CCA active counter is in unit of us. 
                                     This counter is started on rising edge of secondary CCA and stopped on falling edge of secondary CCA,
                                     used for Measurement Secondary CCA is from ((MDRDY&>=40BW)|sED). 
                                     (Secondary channel busy time, 20/40/80/160MHz) The counter is saturated mode.
                                     Enable when PSCCA_TIME_EN = 1
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_ADDR                 BN0_WF_MIB_TOP_M0SDR17_ADDR
#define BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK                 0x00FFFFFF                // S_CCA_TIME[23..0]
#define BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_SHFT                 0

/* =====================================================================================

  ---M0SDR18 (0x820ED000 + 0x50)---

    P_ED_TIME[23..0]             - (RW) Primary ED(Energy Detection) active counter is in unit of us. This counter is started on rising edge of primary ED and stopped on falling edge of primary ED, used for Measurement. Primary CCA is from (pED). The counter is saturated mode.
                                     Enable when PED_TIME_EN = 1
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_ADDR                  BN0_WF_MIB_TOP_M0SDR18_ADDR
#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK                  0x00FFFFFF                // P_ED_TIME[23..0]
#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_SHFT                  0

/* =====================================================================================

  ---M0SDR19 (0x820ED000 + 0x54)---

    CCK_MDRDY_TIME[23..0]        - (RW) CCK MDRDY counter is in unit of us. This counter is started on CCK mode when MDRDY is active and stopped on falling edge of MDRDY, used for Measurement. The counter is saturated mode.
                                     Enable when OFDM_CCK_MDRDY_TIME_EN = 1
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_ADDR             BN0_WF_MIB_TOP_M0SDR19_ADDR
#define BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK             0x00FFFFFF                // CCK_MDRDY_TIME[23..0]
#define BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_SHFT             0

/* =====================================================================================

  ---M0SDR20 (0x820ED000 + 0x58)---

    OFDM_LG_MIXED_VHT_MDRDY_TIME[23..0] - (RW) OFDM_LG_MIXED_VHT_MDRDY_TIME counter is in unit of us. This counter is started on LG/MIXED/VHT mode when MDRDY is active and stopped on falling edge of MDRDY, used for Measurement. The counter is saturated mode.
                                     Enable when OFDM_CCK_MDRDY_TIME_EN = 1
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_ADDR BN0_WF_MIB_TOP_M0SDR20_ADDR
#define BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0x00FFFFFF                // OFDM_LG_MIXED_VHT_MDRDY_TIME[23..0]
#define BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_SHFT 0

/* =====================================================================================

  ---M0SDR21 (0x820ED000 + 0x5C)---

    OFDM_GREEN_MDRDY_TIME[23..0] - (RW) OFDM_GREEN_MDRDY_TIME counter is in unit of us. This counter is started on GREEN mode when MDRDY is active and stopped on falling edge of MDRDY, used for Measurement. The counter is saturated mode.
                                     Enable when OFDM_CCK_MDRDY_TIME_EN = 1
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_ADDR      BN0_WF_MIB_TOP_M0SDR21_ADDR
#define BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK      0x00FFFFFF                // OFDM_GREEN_MDRDY_TIME[23..0]
#define BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_SHFT      0

/* =====================================================================================

  ---M0SDR22 (0x820ED000 + 0x60)---

    RX_AMPDU_COUNT[31..0]        - (RW) This counter shall be incremented when Rx APMDU occurs
                                     Enable when AMPDU_RX_COUNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR22_RX_AMPDU_COUNT_ADDR             BN0_WF_MIB_TOP_M0SDR22_ADDR
#define BN0_WF_MIB_TOP_M0SDR22_RX_AMPDU_COUNT_MASK             0xFFFFFFFF                // RX_AMPDU_COUNT[31..0]
#define BN0_WF_MIB_TOP_M0SDR22_RX_AMPDU_COUNT_SHFT             0

/* =====================================================================================

  ---M0SDR23 (0x820ED000 + 0x64)---

    RX_TOTBYTE_COUNT[31..0]      - (RW) This counter shall count all bytes when Rx APMDU occurs
                                     Enable when AMPDU_RX_COUNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR23_RX_TOTBYTE_COUNT_ADDR           BN0_WF_MIB_TOP_M0SDR23_ADDR
#define BN0_WF_MIB_TOP_M0SDR23_RX_TOTBYTE_COUNT_MASK           0xFFFFFFFF                // RX_TOTBYTE_COUNT[31..0]
#define BN0_WF_MIB_TOP_M0SDR23_RX_TOTBYTE_COUNT_SHFT           0

/* =====================================================================================

  ---M0SDR24 (0x820ED000 + 0x68)---

    RX_VALIDSF_COUNT[23..0]      - (RW) This counter shall be incremented when Rx APMDU valid sub-frame occurs
                                     Enable when AMPDU_RX_COUNT_EN = 1
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR24_RX_VALIDSF_COUNT_ADDR           BN0_WF_MIB_TOP_M0SDR24_ADDR
#define BN0_WF_MIB_TOP_M0SDR24_RX_VALIDSF_COUNT_MASK           0x00FFFFFF                // RX_VALIDSF_COUNT[23..0]
#define BN0_WF_MIB_TOP_M0SDR24_RX_VALIDSF_COUNT_SHFT           0

/* =====================================================================================

  ---M0SDR25 (0x820ED000 + 0x6C)---

    RX_VALIDBYTE_COUNT[31..0]    - (RW) This counter shall count all valid bytes when Rx APMDU valid sub-frame occurs
                                     Enable when AMPDU_RX_COUNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR25_RX_VALIDBYTE_COUNT_ADDR         BN0_WF_MIB_TOP_M0SDR25_ADDR
#define BN0_WF_MIB_TOP_M0SDR25_RX_VALIDBYTE_COUNT_MASK         0xFFFFFFFF                // RX_VALIDBYTE_COUNT[31..0]
#define BN0_WF_MIB_TOP_M0SDR25_RX_VALIDBYTE_COUNT_SHFT         0

/* =====================================================================================

  ---M0SDR26 (0x820ED000 + 0x70)---

    PHY_MIB_COUNT0[31..0]        - (RW) This counter shall be incremented when PHY MIB counter0 indicated +1
                                     Enable when PHY_MIB_COUNT0_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR26_PHY_MIB_COUNT0_ADDR             BN0_WF_MIB_TOP_M0SDR26_ADDR
#define BN0_WF_MIB_TOP_M0SDR26_PHY_MIB_COUNT0_MASK             0xFFFFFFFF                // PHY_MIB_COUNT0[31..0]
#define BN0_WF_MIB_TOP_M0SDR26_PHY_MIB_COUNT0_SHFT             0

/* =====================================================================================

  ---M0SDR27 (0x820ED000 + 0x74)---

    ARB_TX_RWP_FAIL_COUNT[15..0] - (RW) This counter shall increamemt when remaining windows protected package not send
                                     Enable when ARB_TX_RWP_FAIL_COUNT_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR27_ARB_TX_RWP_FAIL_COUNT_ADDR      BN0_WF_MIB_TOP_M0SDR27_ADDR
#define BN0_WF_MIB_TOP_M0SDR27_ARB_TX_RWP_FAIL_COUNT_MASK      0x0000FFFF                // ARB_TX_RWP_FAIL_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR27_ARB_TX_RWP_FAIL_COUNT_SHFT      0

/* =====================================================================================

  ---M0SDR28 (0x820ED000 + 0x78)---

    ARB_TX_RWP_NEED_COUNT[15..0] - (RW) This counter shall increamemt when remaining windows protected package should send
                                     Enable when ARB_TX_RWP_NEED_COUNT_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR28_ARB_TX_RWP_NEED_COUNT_ADDR      BN0_WF_MIB_TOP_M0SDR28_ADDR
#define BN0_WF_MIB_TOP_M0SDR28_ARB_TX_RWP_NEED_COUNT_MASK      0x0000FFFF                // ARB_TX_RWP_NEED_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR28_ARB_TX_RWP_NEED_COUNT_SHFT      0

/* =====================================================================================

  ---M0SDR30 (0x820ED000 + 0x80)---

    VEC_DROP_COUNT[15..0]        - (RW) This counter shall be incremented when a vector was dropped by vector queue overflow.
                                     Enable when VEC_DROP_COUNT_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR30_VEC_DROP_COUNT_ADDR             BN0_WF_MIB_TOP_M0SDR30_ADDR
#define BN0_WF_MIB_TOP_M0SDR30_VEC_DROP_COUNT_MASK             0x0000FFFF                // VEC_DROP_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR30_VEC_DROP_COUNT_SHFT             0

/* =====================================================================================

  ---M0SDR31 (0x820ED000 + 0x84)---

    BA_COUNT[31..0]              - (RW) This counter shall be incremented when Rx get the BA of AMPDU occurs
                                     Enable when AMPDU_TX_COUNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR31_BA_COUNT_ADDR                   BN0_WF_MIB_TOP_M0SDR31_ADDR
#define BN0_WF_MIB_TOP_M0SDR31_BA_COUNT_MASK                   0xFFFFFFFF                // BA_COUNT[31..0]
#define BN0_WF_MIB_TOP_M0SDR31_BA_COUNT_SHFT                   0

/* =====================================================================================

  ---M0SDR32 (0x820ED000 + 0x88)---

    EBF_TX_COUNT[15..0]          - (RW) TX packet transmit with using eBF
                                     Enable when EBFTXINC_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR32_EBF_TX_COUNT_ADDR               BN0_WF_MIB_TOP_M0SDR32_ADDR
#define BN0_WF_MIB_TOP_M0SDR32_EBF_TX_COUNT_MASK               0x0000FFFF                // EBF_TX_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR32_EBF_TX_COUNT_SHFT               0

/* =====================================================================================

  ---M0SDR33 (0x820ED000 + 0x8C)---

    IBF_TX_COUNT[15..0]          - (RW) TX packet transmit with using iBF
                                     Enable when IBFTXINC_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR33_IBF_TX_COUNT_ADDR               BN0_WF_MIB_TOP_M0SDR33_ADDR
#define BN0_WF_MIB_TOP_M0SDR33_IBF_TX_COUNT_MASK               0x0000FFFF                // IBF_TX_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR33_IBF_TX_COUNT_SHFT               0

/* =====================================================================================

  ---M0SDR34 (0x820ED000 + 0x90)---

    MUBF_TX_COUNT[15..0]         - (RW) TX packet transmit with using MUBF
                                     Enable when MUBFTXINC_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_ADDR              BN0_WF_MIB_TOP_M0SDR34_ADDR
#define BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK              0x0000FFFF                // MUBF_TX_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_SHFT              0

/* =====================================================================================

  ---M0SDR35 (0x820ED000 + 0x94)---

    MAC2PHY_TX_TIME[23..0]       - (RW) mac2phy_tx assert time for ap background scan 
                                     (unit: 1us)
                                     Enable when MAC2PHY_TX_TIME_EN = 1
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR35_MAC2PHY_TX_TIME_ADDR            BN0_WF_MIB_TOP_M0SDR35_ADDR
#define BN0_WF_MIB_TOP_M0SDR35_MAC2PHY_TX_TIME_MASK            0x00FFFFFF                // MAC2PHY_TX_TIME[23..0]
#define BN0_WF_MIB_TOP_M0SDR35_MAC2PHY_TX_TIME_SHFT            0

/* =====================================================================================

  ---M0SDR36 (0x820ED000 + 0x98)---

    TXDUR_CNT[23..0]             - (RW) tx duration counter
                                     unit: 1.024us)
                                     Enable when TXDUR_EN = 1
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR36_TXDUR_CNT_ADDR                  BN0_WF_MIB_TOP_M0SDR36_ADDR
#define BN0_WF_MIB_TOP_M0SDR36_TXDUR_CNT_MASK                  0x00FFFFFF                // TXDUR_CNT[23..0]
#define BN0_WF_MIB_TOP_M0SDR36_TXDUR_CNT_SHFT                  0

/* =====================================================================================

  ---M0SDR37 (0x820ED000 + 0x9C)---

    RXDUR_CNT[23..0]             - (RW) rx duration counter
                                     unit: 1.024us)
                                     Enable when RXDUR_EN = 1
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR37_RXDUR_CNT_ADDR                  BN0_WF_MIB_TOP_M0SDR37_ADDR
#define BN0_WF_MIB_TOP_M0SDR37_RXDUR_CNT_MASK                  0x00FFFFFF                // RXDUR_CNT[23..0]
#define BN0_WF_MIB_TOP_M0SDR37_RXDUR_CNT_SHFT                  0

/* =====================================================================================

  ---M0DR0 (0x820ED000 + 0xA0)---

    TX_20MHZ_CNT[15..0]          - (RW) TX packet transmit on 20 MHz
                                     Enable when TX_BW_CNT_EN = 1
    TX_40MHZ_CNT[31..16]         - (RW) TX packet transmit on 40 MHz
                                     Enable when TX_BW_CNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_ADDR                 BN0_WF_MIB_TOP_M0DR0_ADDR
#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK                 0xFFFF0000                // TX_40MHZ_CNT[31..16]
#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT                 16
#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_ADDR                 BN0_WF_MIB_TOP_M0DR0_ADDR
#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK                 0x0000FFFF                // TX_20MHZ_CNT[15..0]
#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_SHFT                 0

/* =====================================================================================

  ---M0DR1 (0x820ED000 + 0xA4)---

    TX_80MHZ_CNT[15..0]          - (RW) TX packet transmit on 80 MHz
                                     Enable when TX_BW_CNT_EN = 1
    TX_160MHZ_CNT[31..16]        - (RW) TX packet transmit on 160 MHz
                                     Enable when TX_BW_CNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_ADDR                BN0_WF_MIB_TOP_M0DR1_ADDR
#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK                0xFFFF0000                // TX_160MHZ_CNT[31..16]
#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT                16
#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_ADDR                 BN0_WF_MIB_TOP_M0DR1_ADDR
#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK                 0x0000FFFF                // TX_80MHZ_CNT[15..0]
#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_SHFT                 0

/* =====================================================================================

  ---M0DR2 (0x820ED000 + 0xA8)---

    TRX_AGG_RANGE0_CNT[15..0]    - (RW) PPDU(A-MPDU) count which Aggregate Size in the range 0 of CR setting
                                     Enable when TRX_AGG_RANGE_CNT_EN = 1
    TRX_AGG_RANGE1_CNT[31..16]   - (RW) PPDU(A-MPDU) count which Aggregate Size in the range 1 of CR setting
                                     Enable when TRX_AGG_RANGE_CNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DR2_TRX_AGG_RANGE1_CNT_ADDR           BN0_WF_MIB_TOP_M0DR2_ADDR
#define BN0_WF_MIB_TOP_M0DR2_TRX_AGG_RANGE1_CNT_MASK           0xFFFF0000                // TRX_AGG_RANGE1_CNT[31..16]
#define BN0_WF_MIB_TOP_M0DR2_TRX_AGG_RANGE1_CNT_SHFT           16
#define BN0_WF_MIB_TOP_M0DR2_TRX_AGG_RANGE0_CNT_ADDR           BN0_WF_MIB_TOP_M0DR2_ADDR
#define BN0_WF_MIB_TOP_M0DR2_TRX_AGG_RANGE0_CNT_MASK           0x0000FFFF                // TRX_AGG_RANGE0_CNT[15..0]
#define BN0_WF_MIB_TOP_M0DR2_TRX_AGG_RANGE0_CNT_SHFT           0

/* =====================================================================================

  ---M0DR3 (0x820ED000 + 0xAC)---

    TRX_AGG_RANGE2_CNT[15..0]    - (RW) PPDU(A-MPDU) count which Aggregate Size in the range 2 of CR setting
                                     Enable when TRX_AGG_RANGE_CNT_EN = 1
    TRX_AGG_RANGE3_CNT[31..16]   - (RW) PPDU(A-MPDU) count which Aggregate Size in the range 3 of CR setting
                                     Enable when TRX_AGG_RANGE_CNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DR3_TRX_AGG_RANGE3_CNT_ADDR           BN0_WF_MIB_TOP_M0DR3_ADDR
#define BN0_WF_MIB_TOP_M0DR3_TRX_AGG_RANGE3_CNT_MASK           0xFFFF0000                // TRX_AGG_RANGE3_CNT[31..16]
#define BN0_WF_MIB_TOP_M0DR3_TRX_AGG_RANGE3_CNT_SHFT           16
#define BN0_WF_MIB_TOP_M0DR3_TRX_AGG_RANGE2_CNT_ADDR           BN0_WF_MIB_TOP_M0DR3_ADDR
#define BN0_WF_MIB_TOP_M0DR3_TRX_AGG_RANGE2_CNT_MASK           0x0000FFFF                // TRX_AGG_RANGE2_CNT[15..0]
#define BN0_WF_MIB_TOP_M0DR3_TRX_AGG_RANGE2_CNT_SHFT           0

/* =====================================================================================

  ---M0DR4 (0x820ED000 + 0xB0)---

    TRX_AGG_RANGE4_CNT[15..0]    - (RW) PPDU(A-MPDU) count which Aggregate Size in the range 4 of CR setting
                                     Enable when TRX_AGG_RANGE_CNT_EN = 1
    TRX_AGG_RANGE5_CNT[31..16]   - (RW) PPDU(A-MPDU) count which Aggregate Size in the range 5 of CR setting
                                     Enable when TRX_AGG_RANGE_CNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DR4_TRX_AGG_RANGE5_CNT_ADDR           BN0_WF_MIB_TOP_M0DR4_ADDR
#define BN0_WF_MIB_TOP_M0DR4_TRX_AGG_RANGE5_CNT_MASK           0xFFFF0000                // TRX_AGG_RANGE5_CNT[31..16]
#define BN0_WF_MIB_TOP_M0DR4_TRX_AGG_RANGE5_CNT_SHFT           16
#define BN0_WF_MIB_TOP_M0DR4_TRX_AGG_RANGE4_CNT_ADDR           BN0_WF_MIB_TOP_M0DR4_ADDR
#define BN0_WF_MIB_TOP_M0DR4_TRX_AGG_RANGE4_CNT_MASK           0x0000FFFF                // TRX_AGG_RANGE4_CNT[15..0]
#define BN0_WF_MIB_TOP_M0DR4_TRX_AGG_RANGE4_CNT_SHFT           0

/* =====================================================================================

  ---M0DR5 (0x820ED000 + 0xB4)---

    TRX_AGG_RANGE6_CNT[15..0]    - (RW) PPDU(A-MPDU) count which Aggregate Size in the range 6 of CR setting
                                     Enable when TRX_AGG_RANGE_CNT_EN = 1
    TRX_AGG_RANGE7_CNT[31..16]   - (RW) PPDU(A-MPDU) count which Aggregate Size in the range 7 of CR setting
                                     Enable when TRX_AGG_RANGE_CNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DR5_TRX_AGG_RANGE7_CNT_ADDR           BN0_WF_MIB_TOP_M0DR5_ADDR
#define BN0_WF_MIB_TOP_M0DR5_TRX_AGG_RANGE7_CNT_MASK           0xFFFF0000                // TRX_AGG_RANGE7_CNT[31..16]
#define BN0_WF_MIB_TOP_M0DR5_TRX_AGG_RANGE7_CNT_SHFT           16
#define BN0_WF_MIB_TOP_M0DR5_TRX_AGG_RANGE6_CNT_ADDR           BN0_WF_MIB_TOP_M0DR5_ADDR
#define BN0_WF_MIB_TOP_M0DR5_TRX_AGG_RANGE6_CNT_MASK           0x0000FFFF                // TRX_AGG_RANGE6_CNT[15..0]
#define BN0_WF_MIB_TOP_M0DR5_TRX_AGG_RANGE6_CNT_SHFT           0

/* =====================================================================================

  ---M0DR6 (0x820ED000 + 0xB8)---

    TX_DDLMT_RNG1_CNT[15..0]     - (RW) Separate reference time (in unit of us) to 5 ranges to count dummy delimiter insertion result
                                     range1: 0 < count < 1/4 ref. time
                                     Enable when DDLMT_TX_EN = 1
    TX_DDLMT_RNG2_CNT[31..16]    - (RW) Separate reference time (in unit of us) to 5 ranges to count dummy delimiter insertion result
                                     range2: 1/4 <= count < 1/2 ref. time
                                     Enable when DDLMT_TX_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_ADDR            BN0_WF_MIB_TOP_M0DR6_ADDR
#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK            0xFFFF0000                // TX_DDLMT_RNG2_CNT[31..16]
#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT            16
#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_ADDR            BN0_WF_MIB_TOP_M0DR6_ADDR
#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK            0x0000FFFF                // TX_DDLMT_RNG1_CNT[15..0]
#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_SHFT            0

/* =====================================================================================

  ---M0DR7 (0x820ED000 + 0xBC)---

    TX_DDLMT_RNG3_CNT[15..0]     - (RW) Separate reference time (in unit of us) to 5 ranges to count dummy delimiter insertion result
                                     range3: 1/2 <= count < 3/4 ref. time
                                     Enable when DDLMT_TX_EN = 1
    TX_DDLMT_RNG4_CNT[31..16]    - (RW) Separate reference time (in unit of us) to 5 ranges to count dummy delimiter insertion result
                                     range4: 3/4 <= count < 1 ref. time
                                     Enable when DDLMT_TX_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_ADDR            BN0_WF_MIB_TOP_M0DR7_ADDR
#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK            0xFFFF0000                // TX_DDLMT_RNG4_CNT[31..16]
#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT            16
#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_ADDR            BN0_WF_MIB_TOP_M0DR7_ADDR
#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK            0x0000FFFF                // TX_DDLMT_RNG3_CNT[15..0]
#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_SHFT            0

/* =====================================================================================

  ---M0DR8 (0x820ED000 + 0XC0)---

    MU_TX_MPDU_CNT[31..0]        - (RW) MU TX ok +TX fail mpdu count
                                     Enable when MU_TXCNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DR8_MU_TX_MPDU_CNT_ADDR               BN0_WF_MIB_TOP_M0DR8_ADDR
#define BN0_WF_MIB_TOP_M0DR8_MU_TX_MPDU_CNT_MASK               0xFFFFFFFF                // MU_TX_MPDU_CNT[31..0]
#define BN0_WF_MIB_TOP_M0DR8_MU_TX_MPDU_CNT_SHFT               0

/* =====================================================================================

  ---M0DR9 (0x820ED000 + 0XC4)---

    MU_TXOK_MPDU_CNT[31..0]      - (RW) MU TX ok mpdu count
                                     Enable when MU_TXCNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DR9_MU_TXOK_MPDU_CNT_ADDR             BN0_WF_MIB_TOP_M0DR9_ADDR
#define BN0_WF_MIB_TOP_M0DR9_MU_TXOK_MPDU_CNT_MASK             0xFFFFFFFF                // MU_TXOK_MPDU_CNT[31..0]
#define BN0_WF_MIB_TOP_M0DR9_MU_TXOK_MPDU_CNT_SHFT             0

/* =====================================================================================

  ---M0DR10 (0x820ED000 + 0XC8)---

    MU_FAIL_PPDU_CNT[15..0]      - (RW) MU to SU ppdu count
                                     Enable when MU_TXCNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_ADDR            BN0_WF_MIB_TOP_M0DR10_ADDR
#define BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK            0x0000FFFF                // MU_FAIL_PPDU_CNT[15..0]
#define BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_SHFT            0

/* =====================================================================================

  ---M0DR11 (0x820ED000 + 0XCC)---

    SU_TXOK_MPDU_CNT[31..0]      - (RW) SU TX ok mpdu count
                                     Enable when SU_TXCNT_EN = 1
                                     calculate with band0 or band1 which base on cr_mu_band_sel

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DR11_SU_TXOK_MPDU_CNT_ADDR            BN0_WF_MIB_TOP_M0DR11_ADDR
#define BN0_WF_MIB_TOP_M0DR11_SU_TXOK_MPDU_CNT_MASK            0xFFFFFFFF                // SU_TXOK_MPDU_CNT[31..0]
#define BN0_WF_MIB_TOP_M0DR11_SU_TXOK_MPDU_CNT_SHFT            0

/* =====================================================================================

  ---M0SDR38 (0x820ED000 + 0xD0)---

    TXCTRL_CNT[23..0]            - (RW) control frame tx counter
                                     Enable when TXCTERL_EN = 1
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR38_TXCTRL_CNT_ADDR                 BN0_WF_MIB_TOP_M0SDR38_ADDR
#define BN0_WF_MIB_TOP_M0SDR38_TXCTRL_CNT_MASK                 0x00FFFFFF                // TXCTRL_CNT[23..0]
#define BN0_WF_MIB_TOP_M0SDR38_TXCTRL_CNT_SHFT                 0

/* =====================================================================================

  ---M0SDR39 (0x820ED000 + 0xD4)---

    MGMT_FRAMERETRY_CNT[23..0]   - (RW) management frame retry counter
                                     Enable when MGMT_FRAMERETRY_CNT_EN = 1
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR39_MGMT_FRAMERETRY_CNT_ADDR        BN0_WF_MIB_TOP_M0SDR39_ADDR
#define BN0_WF_MIB_TOP_M0SDR39_MGMT_FRAMERETRY_CNT_MASK        0x00FFFFFF                // MGMT_FRAMERETRY_CNT[23..0]
#define BN0_WF_MIB_TOP_M0SDR39_MGMT_FRAMERETRY_CNT_SHFT        0

/* =====================================================================================

  ---M0SDR40 (0x820ED000 + 0xD8)---

    DATA_FRAMERETRY_CNT[23..0]   - (RW) data frame retry counter
                                     Enable when DATA_FRAMERETRY_CNT_EN = 1
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR40_DATA_FRAMERETRY_CNT_ADDR        BN0_WF_MIB_TOP_M0SDR40_ADDR
#define BN0_WF_MIB_TOP_M0SDR40_DATA_FRAMERETRY_CNT_MASK        0x00FFFFFF                // DATA_FRAMERETRY_CNT[23..0]
#define BN0_WF_MIB_TOP_M0SDR40_DATA_FRAMERETRY_CNT_SHFT        0

/* =====================================================================================

  ---M0SDR41 (0x820ED000 + 0xDC)---

    RX_NON_NO_DATA_CNT[15..0]    - (RW) For dynamic silence window function used. To increase need to meet second RxV is received completely, and rmac_dsw_rx_data is asserted (refer to DSW SRS). Besides, an A-MPDU only increases once only.
                                     Enable when RX_NON_NO_DATA_CNT_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR41_RX_NON_NO_DATA_CNT_ADDR         BN0_WF_MIB_TOP_M0SDR41_ADDR
#define BN0_WF_MIB_TOP_M0SDR41_RX_NON_NO_DATA_CNT_MASK         0x0000FFFF                // RX_NON_NO_DATA_CNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR41_RX_NON_NO_DATA_CNT_SHFT         0

/* =====================================================================================

  ---M0SDR42 (0x820ED000 + 0xE0)---

    RX_PARTIAL_BCN_CNT0[15..0]   - (RW) This counter shall increment when received partial beacon from bssid0
                                     Enable when RX_PARTIAL_BCN_CNT_EN = 1
    RX_PARTIAL_BCN_CNT1[31..16]  - (RW) This counter shall increment when received partial beacon from bssid1
                                     Enable when RX_PARTIAL_BCN_CNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR42_RX_PARTIAL_BCN_CNT1_ADDR        BN0_WF_MIB_TOP_M0SDR42_ADDR
#define BN0_WF_MIB_TOP_M0SDR42_RX_PARTIAL_BCN_CNT1_MASK        0xFFFF0000                // RX_PARTIAL_BCN_CNT1[31..16]
#define BN0_WF_MIB_TOP_M0SDR42_RX_PARTIAL_BCN_CNT1_SHFT        16
#define BN0_WF_MIB_TOP_M0SDR42_RX_PARTIAL_BCN_CNT0_ADDR        BN0_WF_MIB_TOP_M0SDR42_ADDR
#define BN0_WF_MIB_TOP_M0SDR42_RX_PARTIAL_BCN_CNT0_MASK        0x0000FFFF                // RX_PARTIAL_BCN_CNT0[15..0]
#define BN0_WF_MIB_TOP_M0SDR42_RX_PARTIAL_BCN_CNT0_SHFT        0

/* =====================================================================================

  ---M0SDR43 (0x820ED000 + 0xE4)---

    RX_PARTIAL_BCN_CNT2[15..0]   - (RW) This counter shall increment when received partial beacon from bssid2
                                     Enable when RX_PARTIAL_BCN_CNT_EN = 1
    RX_PARTIAL_BCN_CNT3[31..16]  - (RW) This counter shall increment when received partial beacon from bssid3
                                     Enable when RX_PARTIAL_BCN_CNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR43_RX_PARTIAL_BCN_CNT3_ADDR        BN0_WF_MIB_TOP_M0SDR43_ADDR
#define BN0_WF_MIB_TOP_M0SDR43_RX_PARTIAL_BCN_CNT3_MASK        0xFFFF0000                // RX_PARTIAL_BCN_CNT3[31..16]
#define BN0_WF_MIB_TOP_M0SDR43_RX_PARTIAL_BCN_CNT3_SHFT        16
#define BN0_WF_MIB_TOP_M0SDR43_RX_PARTIAL_BCN_CNT2_ADDR        BN0_WF_MIB_TOP_M0SDR43_ADDR
#define BN0_WF_MIB_TOP_M0SDR43_RX_PARTIAL_BCN_CNT2_MASK        0x0000FFFF                // RX_PARTIAL_BCN_CNT2[15..0]
#define BN0_WF_MIB_TOP_M0SDR43_RX_PARTIAL_BCN_CNT2_SHFT        0

/* =====================================================================================

  ---M0SDR44 (0x820ED000 + 0xE8)---

    ED_LISTEN_ABOVE_CNT[15..0]   - (RW) ED_LISTEN_ABOVE_CNT counter is in unit of us. This counter is started on listen state with energy >= threshold, used for measurement.
                                     Enable when MOZART_ED_TRIG_CNT_EN = 1
    ED_LISTEN_BELOW_CNT[31..16]  - (RW) ED_LISTEN_BELOW_CNT counter is in unit of us. This counter is started on listen state with energy < threshold, used for measurement.
                                     Enable when MOZART_ED_TRIG_CNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR44_ED_LISTEN_BELOW_CNT_ADDR        BN0_WF_MIB_TOP_M0SDR44_ADDR
#define BN0_WF_MIB_TOP_M0SDR44_ED_LISTEN_BELOW_CNT_MASK        0xFFFF0000                // ED_LISTEN_BELOW_CNT[31..16]
#define BN0_WF_MIB_TOP_M0SDR44_ED_LISTEN_BELOW_CNT_SHFT        16
#define BN0_WF_MIB_TOP_M0SDR44_ED_LISTEN_ABOVE_CNT_ADDR        BN0_WF_MIB_TOP_M0SDR44_ADDR
#define BN0_WF_MIB_TOP_M0SDR44_ED_LISTEN_ABOVE_CNT_MASK        0x0000FFFF                // ED_LISTEN_ABOVE_CNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR44_ED_LISTEN_ABOVE_CNT_SHFT        0

/* =====================================================================================

  ---M0SDR45 (0x820ED000 + 0xEC)---

    TX_TIME_CNT[15..0]           - (RW) TX_TIME_CNT counter is in unit of us. This counter is started on transmission state, used for measurement.
                                     Enable when TX_TIME_CNT_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR45_TX_TIME_CNT_ADDR                BN0_WF_MIB_TOP_M0SDR45_ADDR
#define BN0_WF_MIB_TOP_M0SDR45_TX_TIME_CNT_MASK                0x0000FFFF                // TX_TIME_CNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR45_TX_TIME_CNT_SHFT                0

/* =====================================================================================

  ---M0SDR46 (0x820ED000 + 0xF0)---

    OPPO_PS_RX_DIS_CNT[15..0]    - (RW) This counter shall increment when  PPDUs dropped by the oppo_ps_rx_dis mechanism
                                     Enable when OPPO_PS_RX_DIS_CNT_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR46_OPPO_PS_RX_DIS_CNT_ADDR         BN0_WF_MIB_TOP_M0SDR46_ADDR
#define BN0_WF_MIB_TOP_M0SDR46_OPPO_PS_RX_DIS_CNT_MASK         0x0000FFFF                // OPPO_PS_RX_DIS_CNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR46_OPPO_PS_RX_DIS_CNT_SHFT         0

/* =====================================================================================

  ---M0SDR47 (0x820ED000 + 0xF4)---

    OPPO_PS_RX_DIS_TIME_CNT[25..0] - (RW) This counter is in unit of us. This counter is start on oppo_ps_rx_dis state, used for measurement
                                     Enable when OPPO_PS_RX_DIS_TIME_CNT_EN = 1
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR47_OPPO_PS_RX_DIS_TIME_CNT_ADDR    BN0_WF_MIB_TOP_M0SDR47_ADDR
#define BN0_WF_MIB_TOP_M0SDR47_OPPO_PS_RX_DIS_TIME_CNT_MASK    0x03FFFFFF                // OPPO_PS_RX_DIS_TIME_CNT[25..0]
#define BN0_WF_MIB_TOP_M0SDR47_OPPO_PS_RX_DIS_TIME_CNT_SHFT    0

/* =====================================================================================

  ---M0SDR48 (0x820ED000 + 0xF8)---

    OPPO_SX_OFF_CNT[15..0]       - (RW) This counter shall increment when SX power off (OPPO_PS_WINDOW terminate)
                                     Enable when OPPO_SX_OFF_CNT_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR48_OPPO_SX_OFF_CNT_ADDR            BN0_WF_MIB_TOP_M0SDR48_ADDR
#define BN0_WF_MIB_TOP_M0SDR48_OPPO_SX_OFF_CNT_MASK            0x0000FFFF                // OPPO_SX_OFF_CNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR48_OPPO_SX_OFF_CNT_SHFT            0

/* =====================================================================================

  ---M0SDR49 (0x820ED000 + 0xFC)---

    DTIM0_UPDATE_CHK_FAIL_CNT[7..0] - (RW) This counter shall increment when update dtim check fail by bssid0
                                     Enable when DTIM_UPDATE_CHK_FAIL_CNT_EN = 1
    DTIM1_UPDATE_CHK_FAIL_CNT[15..8] - (RW) This counter shall increment when update dtim check fail by bssid1
                                     Enable when DTIM_UPDATE_CHK_FAIL_CNT_EN = 1
    DTIM2_UPDATE_CHK_FAIL_CNT[23..16] - (RW) This counter shall increment when update dtim check fail by bssid2
                                     Enable when DTIM_UPDATE_CHK_FAIL_CNT_EN = 1
    DTIM3_UPDATE_CHK_FAIL_CNT[31..24] - (RW) This counter shall increment when update dtim check fail by bssid3
                                     Enable when DTIM_UPDATE_CHK_FAIL_CNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR49_DTIM3_UPDATE_CHK_FAIL_CNT_ADDR  BN0_WF_MIB_TOP_M0SDR49_ADDR
#define BN0_WF_MIB_TOP_M0SDR49_DTIM3_UPDATE_CHK_FAIL_CNT_MASK  0xFF000000                // DTIM3_UPDATE_CHK_FAIL_CNT[31..24]
#define BN0_WF_MIB_TOP_M0SDR49_DTIM3_UPDATE_CHK_FAIL_CNT_SHFT  24
#define BN0_WF_MIB_TOP_M0SDR49_DTIM2_UPDATE_CHK_FAIL_CNT_ADDR  BN0_WF_MIB_TOP_M0SDR49_ADDR
#define BN0_WF_MIB_TOP_M0SDR49_DTIM2_UPDATE_CHK_FAIL_CNT_MASK  0x00FF0000                // DTIM2_UPDATE_CHK_FAIL_CNT[23..16]
#define BN0_WF_MIB_TOP_M0SDR49_DTIM2_UPDATE_CHK_FAIL_CNT_SHFT  16
#define BN0_WF_MIB_TOP_M0SDR49_DTIM1_UPDATE_CHK_FAIL_CNT_ADDR  BN0_WF_MIB_TOP_M0SDR49_ADDR
#define BN0_WF_MIB_TOP_M0SDR49_DTIM1_UPDATE_CHK_FAIL_CNT_MASK  0x0000FF00                // DTIM1_UPDATE_CHK_FAIL_CNT[15..8]
#define BN0_WF_MIB_TOP_M0SDR49_DTIM1_UPDATE_CHK_FAIL_CNT_SHFT  8
#define BN0_WF_MIB_TOP_M0SDR49_DTIM0_UPDATE_CHK_FAIL_CNT_ADDR  BN0_WF_MIB_TOP_M0SDR49_ADDR
#define BN0_WF_MIB_TOP_M0SDR49_DTIM0_UPDATE_CHK_FAIL_CNT_MASK  0x000000FF                // DTIM0_UPDATE_CHK_FAIL_CNT[7..0]
#define BN0_WF_MIB_TOP_M0SDR49_DTIM0_UPDATE_CHK_FAIL_CNT_SHFT  0

/* =====================================================================================

  ---M0B0SDR0 (0x820ED000 + 0x100)---

    RTSTXCOUNT[15..0]            - (RW) This counter shall increment when RTS is successfully tx.
    RTSRETRYCOUNT[31..16]        - (RW) This counter shall increment when a CTS is not received, or 2nd CTS is rx failed in Dual CTS mode in response to an RTS.

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_ADDR             BN0_WF_MIB_TOP_M0B0SDR0_ADDR
#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK             0xFFFF0000                // RTSRETRYCOUNT[31..16]
#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT             16
#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_ADDR                BN0_WF_MIB_TOP_M0B0SDR0_ADDR
#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK                0x0000FFFF                // RTSTXCOUNT[15..0]
#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_SHFT                0

/* =====================================================================================

  ---M0B0SDR1 (0x820ED000 + 0x104)---

    BAMISSCOUNT[15..0]           - (RW) This counter shall be incremented when the expected BlockAck is not received in response to an Implicit BlockAckReg frame.
    ACKFAILCOUNT[31..16]         - (RW) This counter shall increment when an ACK or BA is not received when expected.

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_ADDR              BN0_WF_MIB_TOP_M0B0SDR1_ADDR
#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK              0xFFFF0000                // ACKFAILCOUNT[31..16]
#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT              16
#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_ADDR               BN0_WF_MIB_TOP_M0B0SDR1_ADDR
#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK               0x0000FFFF                // BAMISSCOUNT[15..0]
#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_SHFT               0

/* =====================================================================================

  ---M0B0SDR2 (0x820ED000 + 0x108)---

    FRAMERETRYCOUNT[15..0]       - (RW) This counter shall increment when an MSDU is successfully             transmitted after one or more retransmissions.
    FRAMERETRY2COUNT[31..16]     - (RW) This counter shall increment when an MSDU is successfully             transmitted after one or more retransmissions.

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_ADDR          BN0_WF_MIB_TOP_M0B0SDR2_ADDR
#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK          0xFFFF0000                // FRAMERETRY2COUNT[31..16]
#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT          16
#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_ADDR           BN0_WF_MIB_TOP_M0B0SDR2_ADDR
#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK           0x0000FFFF                // FRAMERETRYCOUNT[15..0]
#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_SHFT           0

/* =====================================================================================

  ---M0B0SDR3 (0x820ED000 + 0x10C)---

    FRAMERETRY3COUNT[15..0]      - (RW) This counter shall increment when an MSDU is successfully             transmitted after one or more retransmissions.
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_ADDR          BN0_WF_MIB_TOP_M0B0SDR3_ADDR
#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK          0x0000FFFF                // FRAMERETRY3COUNT[15..0]
#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_SHFT          0

/* =====================================================================================

  ---M0B1SDR0 (0x820ED000 + 0x110)---

    RTSTXCOUNT[15..0]            - (RW) This counter shall increment when RTS is successfully tx.
    RTSRETRYCOUNT[31..16]        - (RW) This counter shall increment when a CTS is not received, or 2nd CTS is rx failed in Dual CTS mode in response to an RTS.

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0B1SDR0_RTSRETRYCOUNT_ADDR             BN0_WF_MIB_TOP_M0B1SDR0_ADDR
#define BN0_WF_MIB_TOP_M0B1SDR0_RTSRETRYCOUNT_MASK             0xFFFF0000                // RTSRETRYCOUNT[31..16]
#define BN0_WF_MIB_TOP_M0B1SDR0_RTSRETRYCOUNT_SHFT             16
#define BN0_WF_MIB_TOP_M0B1SDR0_RTSTXCOUNT_ADDR                BN0_WF_MIB_TOP_M0B1SDR0_ADDR
#define BN0_WF_MIB_TOP_M0B1SDR0_RTSTXCOUNT_MASK                0x0000FFFF                // RTSTXCOUNT[15..0]
#define BN0_WF_MIB_TOP_M0B1SDR0_RTSTXCOUNT_SHFT                0

/* =====================================================================================

  ---M0B1SDR1 (0x820ED000 + 0x114)---

    BAMISSCOUNT[15..0]           - (RW) This counter shall be incremented when the expected BlockAck is not received in response to an Implicit BlockAckReg frame.
    ACKFAILCOUNT[31..16]         - (RW) This counter shall increment when an ACK or BA is not received when expected.

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0B1SDR1_ACKFAILCOUNT_ADDR              BN0_WF_MIB_TOP_M0B1SDR1_ADDR
#define BN0_WF_MIB_TOP_M0B1SDR1_ACKFAILCOUNT_MASK              0xFFFF0000                // ACKFAILCOUNT[31..16]
#define BN0_WF_MIB_TOP_M0B1SDR1_ACKFAILCOUNT_SHFT              16
#define BN0_WF_MIB_TOP_M0B1SDR1_BAMISSCOUNT_ADDR               BN0_WF_MIB_TOP_M0B1SDR1_ADDR
#define BN0_WF_MIB_TOP_M0B1SDR1_BAMISSCOUNT_MASK               0x0000FFFF                // BAMISSCOUNT[15..0]
#define BN0_WF_MIB_TOP_M0B1SDR1_BAMISSCOUNT_SHFT               0

/* =====================================================================================

  ---M0B1SDR2 (0x820ED000 + 0x118)---

    FRAMERETRYCOUNT[15..0]       - (RW) This counter shall increment when an MSDU is successfully             transmitted after one or more retransmissions.
    FRAMERETRY2COUNT[31..16]     - (RW) This counter shall increment when an MSDU is successfully             transmitted after one or more retransmissions.

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0B1SDR2_FRAMERETRY2COUNT_ADDR          BN0_WF_MIB_TOP_M0B1SDR2_ADDR
#define BN0_WF_MIB_TOP_M0B1SDR2_FRAMERETRY2COUNT_MASK          0xFFFF0000                // FRAMERETRY2COUNT[31..16]
#define BN0_WF_MIB_TOP_M0B1SDR2_FRAMERETRY2COUNT_SHFT          16
#define BN0_WF_MIB_TOP_M0B1SDR2_FRAMERETRYCOUNT_ADDR           BN0_WF_MIB_TOP_M0B1SDR2_ADDR
#define BN0_WF_MIB_TOP_M0B1SDR2_FRAMERETRYCOUNT_MASK           0x0000FFFF                // FRAMERETRYCOUNT[15..0]
#define BN0_WF_MIB_TOP_M0B1SDR2_FRAMERETRYCOUNT_SHFT           0

/* =====================================================================================

  ---M0B1SDR3 (0x820ED000 + 0x11C)---

    FRAMERETRY3COUNT[15..0]      - (RW) This counter shall increment when an MSDU is successfully             transmitted after one or more retransmissions.
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0B1SDR3_FRAMERETRY3COUNT_ADDR          BN0_WF_MIB_TOP_M0B1SDR3_ADDR
#define BN0_WF_MIB_TOP_M0B1SDR3_FRAMERETRY3COUNT_MASK          0x0000FFFF                // FRAMERETRY3COUNT[15..0]
#define BN0_WF_MIB_TOP_M0B1SDR3_FRAMERETRY3COUNT_SHFT          0

/* =====================================================================================

  ---M0B2SDR0 (0x820ED000 + 0x120)---

    RTSTXCOUNT[15..0]            - (RW) This counter shall increment when RTS is successfully tx.
    RTSRETRYCOUNT[31..16]        - (RW) This counter shall increment when a CTS is not received, or 2nd CTS is rx failed in Dual CTS mode in response to an RTS.

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0B2SDR0_RTSRETRYCOUNT_ADDR             BN0_WF_MIB_TOP_M0B2SDR0_ADDR
#define BN0_WF_MIB_TOP_M0B2SDR0_RTSRETRYCOUNT_MASK             0xFFFF0000                // RTSRETRYCOUNT[31..16]
#define BN0_WF_MIB_TOP_M0B2SDR0_RTSRETRYCOUNT_SHFT             16
#define BN0_WF_MIB_TOP_M0B2SDR0_RTSTXCOUNT_ADDR                BN0_WF_MIB_TOP_M0B2SDR0_ADDR
#define BN0_WF_MIB_TOP_M0B2SDR0_RTSTXCOUNT_MASK                0x0000FFFF                // RTSTXCOUNT[15..0]
#define BN0_WF_MIB_TOP_M0B2SDR0_RTSTXCOUNT_SHFT                0

/* =====================================================================================

  ---M0B2SDR1 (0x820ED000 + 0x124)---

    BAMISSCOUNT[15..0]           - (RW) This counter shall be incremented when the expected BlockAck is not received in response to an Implicit BlockAckReg frame.
    ACKFAILCOUNT[31..16]         - (RW) This counter shall increment when an ACK or BA is not received when expected.

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0B2SDR1_ACKFAILCOUNT_ADDR              BN0_WF_MIB_TOP_M0B2SDR1_ADDR
#define BN0_WF_MIB_TOP_M0B2SDR1_ACKFAILCOUNT_MASK              0xFFFF0000                // ACKFAILCOUNT[31..16]
#define BN0_WF_MIB_TOP_M0B2SDR1_ACKFAILCOUNT_SHFT              16
#define BN0_WF_MIB_TOP_M0B2SDR1_BAMISSCOUNT_ADDR               BN0_WF_MIB_TOP_M0B2SDR1_ADDR
#define BN0_WF_MIB_TOP_M0B2SDR1_BAMISSCOUNT_MASK               0x0000FFFF                // BAMISSCOUNT[15..0]
#define BN0_WF_MIB_TOP_M0B2SDR1_BAMISSCOUNT_SHFT               0

/* =====================================================================================

  ---M0B2SDR2 (0x820ED000 + 0x128)---

    FRAMERETRYCOUNT[15..0]       - (RW) This counter shall increment when an MSDU is successfully             transmitted after one or more retransmissions.
    FRAMERETRY2COUNT[31..16]     - (RW) This counter shall increment when an MSDU is successfully             transmitted after one or more retransmissions.

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0B2SDR2_FRAMERETRY2COUNT_ADDR          BN0_WF_MIB_TOP_M0B2SDR2_ADDR
#define BN0_WF_MIB_TOP_M0B2SDR2_FRAMERETRY2COUNT_MASK          0xFFFF0000                // FRAMERETRY2COUNT[31..16]
#define BN0_WF_MIB_TOP_M0B2SDR2_FRAMERETRY2COUNT_SHFT          16
#define BN0_WF_MIB_TOP_M0B2SDR2_FRAMERETRYCOUNT_ADDR           BN0_WF_MIB_TOP_M0B2SDR2_ADDR
#define BN0_WF_MIB_TOP_M0B2SDR2_FRAMERETRYCOUNT_MASK           0x0000FFFF                // FRAMERETRYCOUNT[15..0]
#define BN0_WF_MIB_TOP_M0B2SDR2_FRAMERETRYCOUNT_SHFT           0

/* =====================================================================================

  ---M0B2SDR3 (0x820ED000 + 0x12C)---

    FRAMERETRY3COUNT[15..0]      - (RW) This counter shall increment when an MSDU is successfully             transmitted after one or more retransmissions.
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0B2SDR3_FRAMERETRY3COUNT_ADDR          BN0_WF_MIB_TOP_M0B2SDR3_ADDR
#define BN0_WF_MIB_TOP_M0B2SDR3_FRAMERETRY3COUNT_MASK          0x0000FFFF                // FRAMERETRY3COUNT[15..0]
#define BN0_WF_MIB_TOP_M0B2SDR3_FRAMERETRY3COUNT_SHFT          0

/* =====================================================================================

  ---M0B3SDR0 (0x820ED000 + 0x130)---

    RTSTXCOUNT[15..0]            - (RW) This counter shall increment when RTS is successfully tx.
    RTSRETRYCOUNT[31..16]        - (RW) This counter shall increment when a CTS is not received, or 2nd CTS is rx failed in Dual CTS mode in response to an RTS.

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0B3SDR0_RTSRETRYCOUNT_ADDR             BN0_WF_MIB_TOP_M0B3SDR0_ADDR
#define BN0_WF_MIB_TOP_M0B3SDR0_RTSRETRYCOUNT_MASK             0xFFFF0000                // RTSRETRYCOUNT[31..16]
#define BN0_WF_MIB_TOP_M0B3SDR0_RTSRETRYCOUNT_SHFT             16
#define BN0_WF_MIB_TOP_M0B3SDR0_RTSTXCOUNT_ADDR                BN0_WF_MIB_TOP_M0B3SDR0_ADDR
#define BN0_WF_MIB_TOP_M0B3SDR0_RTSTXCOUNT_MASK                0x0000FFFF                // RTSTXCOUNT[15..0]
#define BN0_WF_MIB_TOP_M0B3SDR0_RTSTXCOUNT_SHFT                0

/* =====================================================================================

  ---M0B3SDR1 (0x820ED000 + 0x134)---

    BAMISSCOUNT[15..0]           - (RW) This counter shall be incremented when the expected BlockAck is not received in response to an Implicit BlockAckReg frame.
    ACKFAILCOUNT[31..16]         - (RW) This counter shall increment when an ACK or BA is not received when expected.

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0B3SDR1_ACKFAILCOUNT_ADDR              BN0_WF_MIB_TOP_M0B3SDR1_ADDR
#define BN0_WF_MIB_TOP_M0B3SDR1_ACKFAILCOUNT_MASK              0xFFFF0000                // ACKFAILCOUNT[31..16]
#define BN0_WF_MIB_TOP_M0B3SDR1_ACKFAILCOUNT_SHFT              16
#define BN0_WF_MIB_TOP_M0B3SDR1_BAMISSCOUNT_ADDR               BN0_WF_MIB_TOP_M0B3SDR1_ADDR
#define BN0_WF_MIB_TOP_M0B3SDR1_BAMISSCOUNT_MASK               0x0000FFFF                // BAMISSCOUNT[15..0]
#define BN0_WF_MIB_TOP_M0B3SDR1_BAMISSCOUNT_SHFT               0

/* =====================================================================================

  ---M0B3SDR2 (0x820ED000 + 0x138)---

    FRAMERETRYCOUNT[15..0]       - (RW) This counter shall increment when an MSDU is successfully             transmitted after one or more retransmissions.
    FRAMERETRY2COUNT[31..16]     - (RW) This counter shall increment when an MSDU is successfully             transmitted after one or more retransmissions.

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0B3SDR2_FRAMERETRY2COUNT_ADDR          BN0_WF_MIB_TOP_M0B3SDR2_ADDR
#define BN0_WF_MIB_TOP_M0B3SDR2_FRAMERETRY2COUNT_MASK          0xFFFF0000                // FRAMERETRY2COUNT[31..16]
#define BN0_WF_MIB_TOP_M0B3SDR2_FRAMERETRY2COUNT_SHFT          16
#define BN0_WF_MIB_TOP_M0B3SDR2_FRAMERETRYCOUNT_ADDR           BN0_WF_MIB_TOP_M0B3SDR2_ADDR
#define BN0_WF_MIB_TOP_M0B3SDR2_FRAMERETRYCOUNT_MASK           0x0000FFFF                // FRAMERETRYCOUNT[15..0]
#define BN0_WF_MIB_TOP_M0B3SDR2_FRAMERETRYCOUNT_SHFT           0

/* =====================================================================================

  ---M0B3SDR3 (0x820ED000 + 0x13C)---

    FRAMERETRY3COUNT[15..0]      - (RW) This counter shall increment when an MSDU is successfully             transmitted after one or more retransmissions.
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0B3SDR3_FRAMERETRY3COUNT_ADDR          BN0_WF_MIB_TOP_M0B3SDR3_ADDR
#define BN0_WF_MIB_TOP_M0B3SDR3_FRAMERETRY3COUNT_MASK          0x0000FFFF                // FRAMERETRY3COUNT[15..0]
#define BN0_WF_MIB_TOP_M0B3SDR3_FRAMERETRY3COUNT_SHFT          0

/* =====================================================================================

  ---M0DR12 (0x820ED000 + 0x160)---

    TX_DDLMT_RNG0_CNT[15..0]     - (RW) Separate reference time (in unit of us) to 5 ranges to count dummy delimiter insertion result
                                     range0: count = 0 ref. time
                                     Enable when DDLMT_TX_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_ADDR           BN0_WF_MIB_TOP_M0DR12_ADDR
#define BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK           0x0000FFFF                // TX_DDLMT_RNG0_CNT[15..0]
#define BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_SHFT           0

/* =====================================================================================

  ---M0DR13 (0x820ED000 + 0x164)---

    TRX_AGG_RANGE8_CNT[15..0]    - (RW) PPDU(A-MPDU) count which Aggregate Size in the range 8 of CR setting
                                     Enable when TRX_AGG_RANGE_CNT_EN = 1
    TRX_AGG_RANGE9_CNT[31..16]   - (RW) PPDU(A-MPDU) count which Aggregate Size in the range 9 of CR setting
                                     Enable when TRX_AGG_RANGE_CNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DR13_TRX_AGG_RANGE9_CNT_ADDR          BN0_WF_MIB_TOP_M0DR13_ADDR
#define BN0_WF_MIB_TOP_M0DR13_TRX_AGG_RANGE9_CNT_MASK          0xFFFF0000                // TRX_AGG_RANGE9_CNT[31..16]
#define BN0_WF_MIB_TOP_M0DR13_TRX_AGG_RANGE9_CNT_SHFT          16
#define BN0_WF_MIB_TOP_M0DR13_TRX_AGG_RANGE8_CNT_ADDR          BN0_WF_MIB_TOP_M0DR13_ADDR
#define BN0_WF_MIB_TOP_M0DR13_TRX_AGG_RANGE8_CNT_MASK          0x0000FFFF                // TRX_AGG_RANGE8_CNT[15..0]
#define BN0_WF_MIB_TOP_M0DR13_TRX_AGG_RANGE8_CNT_SHFT          0

/* =====================================================================================

  ---M0DR14 (0x820ED000 + 0x168)---

    TRX_AGG_RANGE10_CNT[15..0]   - (RW) PPDU(A-MPDU) count which Aggregate Size in the range 10 of CR setting
                                     Enable when TRX_AGG_RANGE_CNT_EN = 1
    TRX_AGG_RANGE11_CNT[31..16]  - (RW) PPDU(A-MPDU) count which Aggregate Size in the range 11 of CR setting
                                     Enable when TRX_AGG_RANGE_CNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DR14_TRX_AGG_RANGE11_CNT_ADDR         BN0_WF_MIB_TOP_M0DR14_ADDR
#define BN0_WF_MIB_TOP_M0DR14_TRX_AGG_RANGE11_CNT_MASK         0xFFFF0000                // TRX_AGG_RANGE11_CNT[31..16]
#define BN0_WF_MIB_TOP_M0DR14_TRX_AGG_RANGE11_CNT_SHFT         16
#define BN0_WF_MIB_TOP_M0DR14_TRX_AGG_RANGE10_CNT_ADDR         BN0_WF_MIB_TOP_M0DR14_ADDR
#define BN0_WF_MIB_TOP_M0DR14_TRX_AGG_RANGE10_CNT_MASK         0x0000FFFF                // TRX_AGG_RANGE10_CNT[15..0]
#define BN0_WF_MIB_TOP_M0DR14_TRX_AGG_RANGE10_CNT_SHFT         0

/* =====================================================================================

  ---M0DR15 (0x820ED000 + 0x16C)---

    TRX_AGG_RANGE12_CNT[15..0]   - (RW) PPDU(A-MPDU) count which Aggregate Size in the range 12 of CR setting
                                     Enable when TRX_AGG_RANGE_CNT_EN = 1
    TRX_AGG_RANGE13_CNT[31..16]  - (RW) PPDU(A-MPDU) count which Aggregate Size in the range 13 of CR setting
                                     Enable when TRX_AGG_RANGE_CNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DR15_TRX_AGG_RANGE13_CNT_ADDR         BN0_WF_MIB_TOP_M0DR15_ADDR
#define BN0_WF_MIB_TOP_M0DR15_TRX_AGG_RANGE13_CNT_MASK         0xFFFF0000                // TRX_AGG_RANGE13_CNT[31..16]
#define BN0_WF_MIB_TOP_M0DR15_TRX_AGG_RANGE13_CNT_SHFT         16
#define BN0_WF_MIB_TOP_M0DR15_TRX_AGG_RANGE12_CNT_ADDR         BN0_WF_MIB_TOP_M0DR15_ADDR
#define BN0_WF_MIB_TOP_M0DR15_TRX_AGG_RANGE12_CNT_MASK         0x0000FFFF                // TRX_AGG_RANGE12_CNT[15..0]
#define BN0_WF_MIB_TOP_M0DR15_TRX_AGG_RANGE12_CNT_SHFT         0

/* =====================================================================================

  ---M0DR16 (0x820ED000 + 0x170)---

    TRX_AGG_RANGE14_CNT[15..0]   - (RW) PPDU(A-MPDU) count which Aggregate Size in the range 14 of CR setting
                                     Enable when TRX_AGG_RANGE_CNT_EN = 1
    TRX_AGG_RANGE15_CNT[31..16]  - (RW) PPDU(A-MPDU) count which Aggregate Size in the range 15 of CR setting
                                     Enable when TRX_AGG_RANGE_CNT_EN = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DR16_TRX_AGG_RANGE15_CNT_ADDR         BN0_WF_MIB_TOP_M0DR16_ADDR
#define BN0_WF_MIB_TOP_M0DR16_TRX_AGG_RANGE15_CNT_MASK         0xFFFF0000                // TRX_AGG_RANGE15_CNT[31..16]
#define BN0_WF_MIB_TOP_M0DR16_TRX_AGG_RANGE15_CNT_SHFT         16
#define BN0_WF_MIB_TOP_M0DR16_TRX_AGG_RANGE14_CNT_ADDR         BN0_WF_MIB_TOP_M0DR16_ADDR
#define BN0_WF_MIB_TOP_M0DR16_TRX_AGG_RANGE14_CNT_MASK         0x0000FFFF                // TRX_AGG_RANGE14_CNT[15..0]
#define BN0_WF_MIB_TOP_M0DR16_TRX_AGG_RANGE14_CNT_SHFT         0

/* =====================================================================================

  ---M0DROPSR00 (0x820ED000 + 0x190)---

    RTS_DROP_COUNT[15..0]        - (RW) the counter that gets incremented when the RTS Retry limit is reached
    MPDU_RETRY_DROP_COUNT[31..16] - (RW) the counter that gets incremented when the MPDU Retry limit is reached

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DROPSR00_MPDU_RETRY_DROP_COUNT_ADDR   BN0_WF_MIB_TOP_M0DROPSR00_ADDR
#define BN0_WF_MIB_TOP_M0DROPSR00_MPDU_RETRY_DROP_COUNT_MASK   0xFFFF0000                // MPDU_RETRY_DROP_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0DROPSR00_MPDU_RETRY_DROP_COUNT_SHFT   16
#define BN0_WF_MIB_TOP_M0DROPSR00_RTS_DROP_COUNT_ADDR          BN0_WF_MIB_TOP_M0DROPSR00_ADDR
#define BN0_WF_MIB_TOP_M0DROPSR00_RTS_DROP_COUNT_MASK          0x0000FFFF                // RTS_DROP_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0DROPSR00_RTS_DROP_COUNT_SHFT          0

/* =====================================================================================

  ---M0DROPSR01 (0x820ED000 + 0x194)---

    LTO_DROP_COUNT[15..0]        - (RW) the counter that gets incremented when the Life Time Out limit is reached
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0DROPSR01_LTO_DROP_COUNT_ADDR          BN0_WF_MIB_TOP_M0DROPSR01_ADDR
#define BN0_WF_MIB_TOP_M0DROPSR01_LTO_DROP_COUNT_MASK          0x0000FFFF                // LTO_DROP_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0DROPSR01_LTO_DROP_COUNT_SHFT          0

/* =====================================================================================

  ---M0SDR50 (0x820ED000 + 0x1DC)---

    DBNSS_CNT[15..0]             - (RW) This counter shall increment when using double number of space stream
                                     Enable when DBNSS_CNT_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR50_DBNSS_CNT_ADDR                  BN0_WF_MIB_TOP_M0SDR50_ADDR
#define BN0_WF_MIB_TOP_M0SDR50_DBNSS_CNT_MASK                  0x0000FFFF                // DBNSS_CNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR50_DBNSS_CNT_SHFT                  0

/* =====================================================================================

  ---M0SDR51 (0x820ED000 + 0x1E0)---

    RX_FCS_OK_CNT[15..0]         - (RW) This counter shall increment when receive packet with FCS ok
                                     Enable when RX_FCS_OK_CNT_EN = 1
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0SDR51_RX_FCS_OK_CNT_ADDR              BN0_WF_MIB_TOP_M0SDR51_ADDR
#define BN0_WF_MIB_TOP_M0SDR51_RX_FCS_OK_CNT_MASK              0x0000FFFF                // RX_FCS_OK_CNT[15..0]
#define BN0_WF_MIB_TOP_M0SDR51_RX_FCS_OK_CNT_SHFT              0

/* =====================================================================================

  ---MIB_RSVD (0x820ED000 + 0x3FC)---

    B0_RTS_MBSS_11_1F_ON_BSSID0[0] - (RW)  xxx 
    B1_RTS_MBSS_11_1F_ON_BSSID0[1] - (RW)  xxx 
    RESERVED[31..2]              - (RW)  xxx 

 =====================================================================================*/
#define BN0_WF_MIB_TOP_MIB_RSVD_B1_RTS_MBSS_11_1F_ON_BSSID0_ADDR BN0_WF_MIB_TOP_MIB_RSVD_ADDR
#define BN0_WF_MIB_TOP_MIB_RSVD_B1_RTS_MBSS_11_1F_ON_BSSID0_MASK 0x00000002                // B1_RTS_MBSS_11_1F_ON_BSSID0[1]
#define BN0_WF_MIB_TOP_MIB_RSVD_B1_RTS_MBSS_11_1F_ON_BSSID0_SHFT 1
#define BN0_WF_MIB_TOP_MIB_RSVD_B0_RTS_MBSS_11_1F_ON_BSSID0_ADDR BN0_WF_MIB_TOP_MIB_RSVD_ADDR
#define BN0_WF_MIB_TOP_MIB_RSVD_B0_RTS_MBSS_11_1F_ON_BSSID0_MASK 0x00000001                // B0_RTS_MBSS_11_1F_ON_BSSID0[0]
#define BN0_WF_MIB_TOP_MIB_RSVD_B0_RTS_MBSS_11_1F_ON_BSSID0_SHFT 0

/* =====================================================================================

  ---M0NSS1MCS0 (0x820ED000 + 0x400)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 1 and MSC = 0
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 1 and MSC = 0

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS1MCS0_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS1MCS0_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS0_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS1MCS0_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS1MCS0_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS1MCS0_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS0_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS1MCS0_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS1MCS1 (0x820ED000 + 0x404)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 1 and MSC = 1
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 1 and MSC = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS1MCS1_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS1MCS1_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS1_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS1MCS1_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS1MCS1_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS1MCS1_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS1_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS1MCS1_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS1MCS2 (0x820ED000 + 0x408)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 1 and MSC = 2
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 1 and MSC = 2

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS1MCS2_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS1MCS2_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS2_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS1MCS2_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS1MCS2_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS1MCS2_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS2_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS1MCS2_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS1MCS3 (0x820ED000 + 0x40C)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 1 and MSC = 3
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 1 and MSC = 3

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS1MCS3_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS1MCS3_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS3_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS1MCS3_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS1MCS3_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS1MCS3_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS3_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS1MCS3_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS1MCS4 (0x820ED000 + 0x410)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 1 and MSC = 4
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 1 and MSC = 4

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS1MCS4_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS1MCS4_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS4_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS1MCS4_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS1MCS4_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS1MCS4_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS4_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS1MCS4_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS1MCS5 (0x820ED000 + 0x414)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 1 and MSC = 5
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 1 and MSC = 5

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS1MCS5_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS1MCS5_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS5_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS1MCS5_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS1MCS5_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS1MCS5_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS5_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS1MCS5_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS1MCS6 (0x820ED000 + 0x418)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 1 and MSC = 6
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 1 and MSC = 6

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS1MCS6_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS1MCS6_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS6_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS1MCS6_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS1MCS6_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS1MCS6_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS6_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS1MCS6_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS1MCS7 (0x820ED000 + 0x41C)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 1 and MSC = 7
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 1 and MSC = 7

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS1MCS7_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS1MCS7_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS7_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS1MCS7_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS1MCS7_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS1MCS7_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS7_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS1MCS7_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS1MCS8 (0x820ED000 + 0x420)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 1 and MSC = 8
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 1 and MSC = 8

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS1MCS8_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS1MCS8_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS8_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS1MCS8_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS1MCS8_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS1MCS8_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS8_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS1MCS8_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS1MCS9 (0x820ED000 + 0x424)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 1 and MSC = 9
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 1 and MSC = 9

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS1MCS9_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS1MCS9_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS9_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS1MCS9_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS1MCS9_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS1MCS9_ADDR
#define BN0_WF_MIB_TOP_M0NSS1MCS9_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS1MCS9_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS2MCS0 (0x820ED000 + 0x428)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 2 and MSC = 0
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 2 and MSC = 0

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS2MCS0_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS2MCS0_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS0_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS2MCS0_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS2MCS0_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS2MCS0_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS0_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS2MCS0_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS2MCS1 (0x820ED000 + 0x42c)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 2 and MSC = 1
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 2 and MSC = 1

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS2MCS1_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS2MCS1_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS1_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS2MCS1_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS2MCS1_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS2MCS1_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS1_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS2MCS1_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS2MCS2 (0x820ED000 + 0x430)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 2 and MSC = 2
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 2 and MSC = 2

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS2MCS2_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS2MCS2_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS2_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS2MCS2_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS2MCS2_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS2MCS2_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS2_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS2MCS2_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS2MCS3 (0x820ED000 + 0x434)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 2 and MSC = 3
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 2 and MSC = 3

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS2MCS3_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS2MCS3_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS3_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS2MCS3_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS2MCS3_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS2MCS3_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS3_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS2MCS3_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS2MCS4 (0x820ED000 + 0x438)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 2 and MSC = 4
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 2 and MSC = 4

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS2MCS4_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS2MCS4_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS4_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS2MCS4_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS2MCS4_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS2MCS4_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS4_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS2MCS4_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS2MCS5 (0x820ED000 + 0x43c)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 2 and MSC = 5
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 2 and MSC = 5

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS2MCS5_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS2MCS5_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS5_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS2MCS5_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS2MCS5_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS2MCS5_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS5_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS2MCS5_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS2MCS6 (0x820ED000 + 0x440)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 2 and MSC = 6
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 2 and MSC = 6

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS2MCS6_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS2MCS6_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS6_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS2MCS6_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS2MCS6_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS2MCS6_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS6_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS2MCS6_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS2MCS7 (0x820ED000 + 0x444)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 2 and MSC = 7
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 2 and MSC = 7

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS2MCS7_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS2MCS7_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS7_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS2MCS7_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS2MCS7_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS2MCS7_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS7_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS2MCS7_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS2MCS8 (0x820ED000 + 0x448)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 2 and MSC = 8
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 2 and MSC = 8

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS2MCS8_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS2MCS8_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS8_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS2MCS8_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS2MCS8_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS2MCS8_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS8_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS2MCS8_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0NSS2MCS9 (0x820ED000 + 0x44c)---

    FCS_OK_COUNT[15..0]          - (RW) This counter increments one when RX VHT MU with FCS OK and NSS = 2 and MSC = 9
    FCS_ERR_COUNT[31..16]        - (RW) This counter increments one when RX VHT MU with FCS ERROR and NSS = 2 and MSC = 9

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0NSS2MCS9_FCS_ERR_COUNT_ADDR           BN0_WF_MIB_TOP_M0NSS2MCS9_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS9_FCS_ERR_COUNT_MASK           0xFFFF0000                // FCS_ERR_COUNT[31..16]
#define BN0_WF_MIB_TOP_M0NSS2MCS9_FCS_ERR_COUNT_SHFT           16
#define BN0_WF_MIB_TOP_M0NSS2MCS9_FCS_OK_COUNT_ADDR            BN0_WF_MIB_TOP_M0NSS2MCS9_ADDR
#define BN0_WF_MIB_TOP_M0NSS2MCS9_FCS_OK_COUNT_MASK            0x0000FFFF                // FCS_OK_COUNT[15..0]
#define BN0_WF_MIB_TOP_M0NSS2MCS9_FCS_OK_COUNT_SHFT            0

/* =====================================================================================

  ---M0TABT0 (0x820ED000 + 0x4A0)---

    TX_ABORT_COUNTER_0[15..0]    - (RW) This counter increments one when the abort source selected by CABT0[7:0] occurs
    TX_ABORT_COUNTER_1[31..16]   - (RW) This counter increments one when the abort source selected by CABT0[15:8] occurs

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0TABT0_TX_ABORT_COUNTER_1_ADDR         BN0_WF_MIB_TOP_M0TABT0_ADDR
#define BN0_WF_MIB_TOP_M0TABT0_TX_ABORT_COUNTER_1_MASK         0xFFFF0000                // TX_ABORT_COUNTER_1[31..16]
#define BN0_WF_MIB_TOP_M0TABT0_TX_ABORT_COUNTER_1_SHFT         16
#define BN0_WF_MIB_TOP_M0TABT0_TX_ABORT_COUNTER_0_ADDR         BN0_WF_MIB_TOP_M0TABT0_ADDR
#define BN0_WF_MIB_TOP_M0TABT0_TX_ABORT_COUNTER_0_MASK         0x0000FFFF                // TX_ABORT_COUNTER_0[15..0]
#define BN0_WF_MIB_TOP_M0TABT0_TX_ABORT_COUNTER_0_SHFT         0

/* =====================================================================================

  ---M0TABT1 (0x820ED000 + 0x4A4)---

    TX_ABORT_COUNTER_2[15..0]    - (RW) This counter increments one when the abort source selected by CABT0[23:16] occurs
    TX_ABORT_COUNTER_3[31..16]   - (RW) This counter increments one when the abort source selected by CABT0[31:24] occurs

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0TABT1_TX_ABORT_COUNTER_3_ADDR         BN0_WF_MIB_TOP_M0TABT1_ADDR
#define BN0_WF_MIB_TOP_M0TABT1_TX_ABORT_COUNTER_3_MASK         0xFFFF0000                // TX_ABORT_COUNTER_3[31..16]
#define BN0_WF_MIB_TOP_M0TABT1_TX_ABORT_COUNTER_3_SHFT         16
#define BN0_WF_MIB_TOP_M0TABT1_TX_ABORT_COUNTER_2_ADDR         BN0_WF_MIB_TOP_M0TABT1_ADDR
#define BN0_WF_MIB_TOP_M0TABT1_TX_ABORT_COUNTER_2_MASK         0x0000FFFF                // TX_ABORT_COUNTER_2[15..0]
#define BN0_WF_MIB_TOP_M0TABT1_TX_ABORT_COUNTER_2_SHFT         0

/* =====================================================================================

  ---M0TABT2 (0x820ED000 + 0x4A8)---

    TX_ABORT_COUNTER_4[15..0]    - (RW) This counter increments one when the abort source selected by CABT1[7:0] occurs
    TX_ABORT_COUNTER_5[31..16]   - (RW) This counter increments one when the abort source selected by CABT1[15:8] occurs

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0TABT2_TX_ABORT_COUNTER_5_ADDR         BN0_WF_MIB_TOP_M0TABT2_ADDR
#define BN0_WF_MIB_TOP_M0TABT2_TX_ABORT_COUNTER_5_MASK         0xFFFF0000                // TX_ABORT_COUNTER_5[31..16]
#define BN0_WF_MIB_TOP_M0TABT2_TX_ABORT_COUNTER_5_SHFT         16
#define BN0_WF_MIB_TOP_M0TABT2_TX_ABORT_COUNTER_4_ADDR         BN0_WF_MIB_TOP_M0TABT2_ADDR
#define BN0_WF_MIB_TOP_M0TABT2_TX_ABORT_COUNTER_4_MASK         0x0000FFFF                // TX_ABORT_COUNTER_4[15..0]
#define BN0_WF_MIB_TOP_M0TABT2_TX_ABORT_COUNTER_4_SHFT         0

/* =====================================================================================

  ---M0TABT3 (0x820ED000 + 0x4AC)---

    TX_ABORT_COUNTER_6[15..0]    - (RW) This counter increments one when the abort source selected by CABT1[23:16] occurs
    TX_ABORT_COUNTER_7[31..16]   - (RW) This counter increments one when the abort source selected by CABT1[31:24] occurs

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0TABT3_TX_ABORT_COUNTER_7_ADDR         BN0_WF_MIB_TOP_M0TABT3_ADDR
#define BN0_WF_MIB_TOP_M0TABT3_TX_ABORT_COUNTER_7_MASK         0xFFFF0000                // TX_ABORT_COUNTER_7[31..16]
#define BN0_WF_MIB_TOP_M0TABT3_TX_ABORT_COUNTER_7_SHFT         16
#define BN0_WF_MIB_TOP_M0TABT3_TX_ABORT_COUNTER_6_ADDR         BN0_WF_MIB_TOP_M0TABT3_ADDR
#define BN0_WF_MIB_TOP_M0TABT3_TX_ABORT_COUNTER_6_MASK         0x0000FFFF                // TX_ABORT_COUNTER_6[15..0]
#define BN0_WF_MIB_TOP_M0TABT3_TX_ABORT_COUNTER_6_SHFT         0

/* =====================================================================================

  ---M0CABT0 (0x820ED000 + 0x4B0)---

    TX_ABORT_SRC_SEL_0[6..0]     - (RW) Select the source of TX Abort from AGG, TMAC and ARB HW modules
    TX_ABORT_EN_0[7]             - (RW) Enable or disable TX Abort Counting
    TX_ABORT_SRC_SEL_1[14..8]    - (RW) Select the source of TX Abort from AGG, TMAC and ARB HW modules
    TX_ABORT_EN_1[15]            - (RW) Enable or disable TX Abort Counting
    TX_ABORT_SRC_SEL_2[22..16]   - (RW) Select the source of TX Abort from AGG, TMAC and ARB HW modules
    TX_ABORT_EN_2[23]            - (RW) Enable or disable TX Abort Counting
    TX_ABORT_SRC_SEL_3[30..24]   - (RW) Select the source of TX Abort from AGG, TMAC and ARB HW modules:
                                     set it to 68 to select the abort source - agg_tx_end to ARB : Use tx_abort instead of CF end 
                                     set it to 67 to select the abort source - agg_tx_end to ARB : request time out  when prime user enter pdupre state for MU 
                                     set it to 66 to select the abort source - agg_tx_end to ARB : Hif Error of TXD
                                     set it to 65 to select the abort source - agg_tx_end to ARB : TMAC cannot support CF end during when  agg_dynbw_sreq
                                     set it to 64 to select the abort source - agg_tx_end to ARB : arb_tx_start but agg_ch is not idle
                                     set it to 63 to select the abort source - agg_tx_end to ARB : PTA Packet TX Done
                                     set it to 62 to select the abort source - agg_tx_end to ARB : Do nothing and back to idle 
                                     set it to 61 to select the abort source - agg_tx_end to ARB : Use tx_abort instead of CF end 
                                     set it to 60 to select the abort source - agg_tx_end to ARB : request time out  when prime user enter pdupre state for MU 
                                     set it to 59 to select the abort source - agg_tx_end to ARB : Hif Error of TXD
                                     set it to 58 to select the abort source - agg_tx_end to ARB : TMAC cannot support CF end during when  agg_dynbw_sreq
                                     set it to 57 to select the abort source - agg_tx_end to ARB : arb_tx_start but agg_ch is not idle
                                     set it to 56 to select the abort source - agg_tx_end to ARB : PTA Packet TX Done
                                     set it to 55 to select the abort source - agg_tx_end to ARB : Do nothing and back to idle 
                                     set it to 54 to select the abort source - agg_tx_end to ARB : Use tx_abort instead of CF end 
                                     set it to 53 to select the abort source - agg_tx_end to ARB : request time out  when prime user enter pdupre state for MU 
                                     set it to 52 to select the abort source - agg_tx_end to ARB : Hif Error of TXD
                                     set it to 51 to select the abort source - agg_tx_end to ARB : TMAC cannot support CF end during when  agg_dynbw_sreq
                                     set it to 50 to select the abort source - agg_tx_end to ARB : arb_tx_start but agg_ch is not idle
                                     set it to 49 to select the abort source - agg_tx_end to ARB : PTA Packet TX Done
                                     set it to 48 to select the abort source - agg_tx_end to ARB      : Do nothing and back to idle 
                                     set it to 47 to select the abort source - agg_tx_end to ARB      : Use tx_abort instead of CF end 
                                     set it to 46 to select the abort source - agg_tx_end to ARB      : request time out  when prime user enter pdupre state for MU 
                                     set it to 45 to select the abort source - agg_tx_end to ARB      : Hif Error of TXD
                                     set it to 44 to select the abort source - agg_tx_end to ARB      : TMAC cannot support CF end during when  agg_dynbw_sreq
                                     set it to 43 to select the abort source - agg_tx_end to ARB      : arb_tx_start but agg_ch is not idle
                                     set it to 42 to select the abort source - agg_tx_end to ARB      : PTA Packet TX Done
                                     set it to 41 to select the abort source - agg_tx_end to ARB      : Do nothing and back to idle 
                                     set it to 40 to select the abort source - agg_tx_end to ARB      : arb_tx_start but agg is not idle 
                                     set it to 39 to select the abort source - agg_tx_end to ARB      : arb_tx_start but agg is not idle 
                                     set it to 38 to select the abort source - agg_tx_end to ARB      : Last BW change error 
                                     set it to 37 to select the abort source - agg_tx_end to ARB      : Last BW change error 
                                     set it to 36 to select the abort source - agg_tx_end to ARB      : arb_tx_start but agg ch is not idle at MU mode
                                     set it to 35 to select the abort source - agg_tx_end to ARB      : arb_tx_start but agg ch is not idle at MU mode
                                     set it to 34 to select the abort source - agg_tx_end to ARB      : PPDU send request early
                                     set it to 33 to select the abort source - agg_tx_end to ARB      : PPDU send request early
                                     set it to 32 to select the abort source - tmac_abort to RMAC    : TOD abort
                                     set it to 31 to select the abort source - tmac_abort to RMAC    : TOA abort
                                     set it to 30 to select the abort source - tmac_abort to ARB/TMAC : tfsm rst_Tx (TMAC tx is disabled by ARB or LP)
                                     set it to 29 to select the abort source - tmac_abort to ARB/TMAC : tfsm tx_err_rise (PHY underrun)
                                     set it to 28 to select the abort source - tmac_abort to ARB/TMAC : tfsm rx_busy when I2T check
                                     set it to 27 to select the abort source - tmac_abort to ARB/TMAC : tfsm rts fail (Tx RTS and didn't Rx CTS)
                                     set it to 26 to select the abort source - tmac_abort to ARB/TMAC : tfsm arb keep txop, but txop clear condition happened 
                                     set it to 25 to select the abort source - tmac_abort to ARB/TMAC : tfsm edcf win clear before tx_fsm_cs return to idle
                                     set it to 24 to select the abort source - tmac_abort to ARB/TMAC : tfsm psmp utt windows, rmac notice psmp end
                                     set it to 23 to select the abort source - tmac_abort to ARB/TMAC : tfsm edcca stop TXOP, edcca stop RDG responder
                                     set it to 22 to select the abort source - tmac_abort to ARB/TMAC : tfsm etxbf_abort (ETXBF send BFEE packet, and Tx/Rx happened the same time)
                                     set it to 21 to select the abort source - tmac_abort to ARB/TMAC : tfsm mixed mode/vht mode legacy legnth overflow
                                     set it to 20 to select the abort source - tmac_abort to ARB/TMAC : tfsm no ack (Tx packet and didn't receive ACK)
                                     set it to 19 to select the abort source - tmac_abort to ARB/TMAC : tfsm r2t or t2t TR2T delay condition abnormal stop
                                     set it to 18 to select the abort source - tmac_abort to ARB/TMAC : tfsm receive RDG packet, cannot get WTBL matching before TXV_TOUT
                                     set it to 17 to select the abort source - tmac_abort to ARB      : mdrdy rise at I2T (When I2T check, MDRDY rise)
                                     set it to 16 to select the abort source - tmac_abort to ARB      : tx predownload abort (cca or mdrdy at predownload)
                                     set it to 15 to select the abort source - tmac_abort to TMAC     : tfsm zero handoff but drop response packet or RDG responder
                                     set it to 14 to select the abort source - tmac_abort to TMAC     : tfsm CTS response but stop
                                     set it to 13 to select the abort source - tmac_abort to TMAC     : tfsm arb_tmac_abort
                                     set it to 12 to select the abort source - tmac_abort to ARB    : or (tmac_abort_cond1, tmac_abort_cond2)
                                     set it to 11 to select the abort source - tmac_abort to TMAC     : internal tfsm OR (tmac_abort_cond1, tmac_abort_cond3_g1)
                                     set it to 10 to select the abort source - tmac_abort to TMAC     : internal tfsm OR (tmac_abort_cond1, tmac_abort_cond3_g2)
                                     set it to 09 to select the abort source - tmac_abort to ETXBF    : abort to ETXBF module
                                     set it to 08 to select the abort source - arb_abort              : Queue Stop: The packet being transmitted will be aborted due to queue stop.
                                     set it to 07 to select the abort source - arb_abort              : Queue Flush: The packet being transmitted will be aborted due to queue flush.
                                     set it to 06 to select the abort source - arb_abort              : TX Entry: The packet being transmitted will be aborted if the entry address is equal to WLAN index.
                                     set it to 05 to select the abort source - arb_abort              : Trap: LP Trap that causes abort at specific TSF time in LP if a packet of specific queue is being transmitted.
                                     set it to 04 to select the abort source - arb_abort              : LP Quiet Phase: The packet being transmitted will be aborted if the TSF time in LP matches the quiet phase.
                                     set it to 03 to select the abort source - arb_abort              : pta_tx_req_abort:  TX is not granted by PTA.
                                     set it to 02 to select the abort source - arb_abort              : pta_rx_req_abort: RX is not granted by PTA.
                                     set it to 01 to select the abort source - arb_abort              : cts2self: CTS2Self:reissue aborts TXOP
                                     set it to 00 to select the abort source - arb_abort              : arb0/1_tx_sx_abort: Synthesizer not ready
    TX_ABORT_EN_3[31]            - (RW) Enable or disable TX Abort Counting

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_EN_3_ADDR              BN0_WF_MIB_TOP_M0CABT0_ADDR
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_EN_3_MASK              0x80000000                // TX_ABORT_EN_3[31]
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_EN_3_SHFT              31
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_SRC_SEL_3_ADDR         BN0_WF_MIB_TOP_M0CABT0_ADDR
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_SRC_SEL_3_MASK         0x7F000000                // TX_ABORT_SRC_SEL_3[30..24]
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_SRC_SEL_3_SHFT         24
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_EN_2_ADDR              BN0_WF_MIB_TOP_M0CABT0_ADDR
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_EN_2_MASK              0x00800000                // TX_ABORT_EN_2[23]
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_EN_2_SHFT              23
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_SRC_SEL_2_ADDR         BN0_WF_MIB_TOP_M0CABT0_ADDR
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_SRC_SEL_2_MASK         0x007F0000                // TX_ABORT_SRC_SEL_2[22..16]
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_SRC_SEL_2_SHFT         16
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_EN_1_ADDR              BN0_WF_MIB_TOP_M0CABT0_ADDR
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_EN_1_MASK              0x00008000                // TX_ABORT_EN_1[15]
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_EN_1_SHFT              15
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_SRC_SEL_1_ADDR         BN0_WF_MIB_TOP_M0CABT0_ADDR
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_SRC_SEL_1_MASK         0x00007F00                // TX_ABORT_SRC_SEL_1[14..8]
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_SRC_SEL_1_SHFT         8
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_EN_0_ADDR              BN0_WF_MIB_TOP_M0CABT0_ADDR
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_EN_0_MASK              0x00000080                // TX_ABORT_EN_0[7]
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_EN_0_SHFT              7
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_SRC_SEL_0_ADDR         BN0_WF_MIB_TOP_M0CABT0_ADDR
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_SRC_SEL_0_MASK         0x0000007F                // TX_ABORT_SRC_SEL_0[6..0]
#define BN0_WF_MIB_TOP_M0CABT0_TX_ABORT_SRC_SEL_0_SHFT         0

/* =====================================================================================

  ---M0CABT1 (0x820ED000 + 0x4B4)---

    TX_ABORT_SRC_SEL_4[6..0]     - (RW) Select the source of TX Abort from AGG, TMAC and ARB HW modules
    TX_ABORT_EN_4[7]             - (RW) Enable or disable TX Abort Counting
    TX_ABORT_SRC_SEL_5[14..8]    - (RW) Select the source of TX Abort from AGG, TMAC and ARB HW modules
    TX_ABORT_EN_5[15]            - (RW) Enable or disable TX Abort Counting
    TX_ABORT_SRC_SEL_6[22..16]   - (RW) Select the source of TX Abort from AGG, TMAC and ARB HW modules
    TX_ABORT_EN_6[23]            - (RW) Enable or disable TX Abort Counting
    TX_ABORT_SRC_SEL_7[30..24]   - (RW) Select the source of TX Abort from AGG, TMAC and ARB HW modules
    TX_ABORT_EN_7[31]            - (RW) Enable or disable TX Abort Counting

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_EN_7_ADDR              BN0_WF_MIB_TOP_M0CABT1_ADDR
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_EN_7_MASK              0x80000000                // TX_ABORT_EN_7[31]
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_EN_7_SHFT              31
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_SRC_SEL_7_ADDR         BN0_WF_MIB_TOP_M0CABT1_ADDR
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_SRC_SEL_7_MASK         0x7F000000                // TX_ABORT_SRC_SEL_7[30..24]
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_SRC_SEL_7_SHFT         24
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_EN_6_ADDR              BN0_WF_MIB_TOP_M0CABT1_ADDR
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_EN_6_MASK              0x00800000                // TX_ABORT_EN_6[23]
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_EN_6_SHFT              23
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_SRC_SEL_6_ADDR         BN0_WF_MIB_TOP_M0CABT1_ADDR
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_SRC_SEL_6_MASK         0x007F0000                // TX_ABORT_SRC_SEL_6[22..16]
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_SRC_SEL_6_SHFT         16
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_EN_5_ADDR              BN0_WF_MIB_TOP_M0CABT1_ADDR
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_EN_5_MASK              0x00008000                // TX_ABORT_EN_5[15]
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_EN_5_SHFT              15
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_SRC_SEL_5_ADDR         BN0_WF_MIB_TOP_M0CABT1_ADDR
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_SRC_SEL_5_MASK         0x00007F00                // TX_ABORT_SRC_SEL_5[14..8]
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_SRC_SEL_5_SHFT         8
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_EN_4_ADDR              BN0_WF_MIB_TOP_M0CABT1_ADDR
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_EN_4_MASK              0x00000080                // TX_ABORT_EN_4[7]
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_EN_4_SHFT              7
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_SRC_SEL_4_ADDR         BN0_WF_MIB_TOP_M0CABT1_ADDR
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_SRC_SEL_4_MASK         0x0000007F                // TX_ABORT_SRC_SEL_4[6..0]
#define BN0_WF_MIB_TOP_M0CABT1_TX_ABORT_SRC_SEL_4_SHFT         0

/* =====================================================================================

  ---M0ARNG0 (0x820ED000 + 0x4B8)---

    AGG_RANG_SEL_0[7..0]         - (RW) when TRX_ARNG_MODE = 2'b01,
                                         increase TRX_AGG_RANGE1_CNT when  AGG_RANGE_SEL_0 >= TX_AGG_CNT &     
                                         increase TRX_AGG_RANGE2_CNT when  AGG_RANGE_SEL_1 >= TX_AGG_CNT & TX_AGG_CNT > AGG_RANGE_SEL_0 
                                         increase TRX_AGG_RANGE3_CNT when  AGG_RANGE_SEL_2 >= TX_AGG_CNT & TX_AGG_CNT > AGG_RANGE_SEL_1 
                                         increase TRX_AGG_RANGE4_CNT when                                  TX_AGG_CNT > AGG_RANGE_SEL_2 
                                     
                                         increase TRX_AGG_RANGE5_CNT when  AGG_RANGE_SEL_3 >= RX_AGG_CNT                                
                                         increase TRX_AGG_RANGE6_CNT when  AGG_RANGE_SEL_4 >= RX_AGG_CNT & RX_AGG_CNT > AGG_RANGE_SEL_3 
                                         increase TRX_AGG_RANGE7_CNT when  AGG_RANGE_SEL_5 >= RX_AGG_CNT & RX_AGG_CNT > AGG_RANGE_SEL_4 
                                         increase TRX_AGG_RANGE8_CNT when                                  RX_AGG_CNT > AGG_RANGE_SEL_5
                                     
                                         Note: AGG_RANGE_SEL_6 is not used
                                     
                                     when TRX_ARNG_MODE = 2'b00 or 2'b10:
                                         increase TRX_AGG_RANGE1_CNT when  AGG_RANGE_SEL_0 >= TRX_AGG_CNT &     
                                         increase TRX_AGG_RANGE2_CNT when  AGG_RANGE_SEL_1 >= TRX_AGG_CNT & TRX_AGG_CNT > AGG_RANGE_SEL_0 
                                         increase TRX_AGG_RANGE3_CNT when  AGG_RANGE_SEL_2 >= TRX_AGG_CNT & TRX_AGG_CNT > AGG_RANGE_SEL_1 
                                         increase TRX_AGG_RANGE4_CNT when  AGG_RANGE_SEL_3 >= TRX_AGG_CNT & TRX_AGG_CNT > AGG_RANGE_SEL_2 
                                         increase TRX_AGG_RANGE5_CNT when  AGG_RANGE_SEL_4 >= TRX_AGG_CNT & TRX_AGG_CNT > AGG_RANGE_SEL_3 
                                         increase TRX_AGG_RANGE6_CNT when  AGG_RANGE_SEL_5 >= TRX_AGG_CNT & TRX_AGG_CNT > AGG_RANGE_SEL_4 
                                         increase TRX_AGG_RANGE7_CNT when  AGG_RANGE_SEL_6 >= TRX_AGG_CNT & TRX_AGG_CNT > AGG_RANGE_SEL_5 
                                         increase TRX_AGG_RANGE8_CNT when                                 & TRX_AGG_CNT > AGG_RANGE_SEL_6
    AGG_RANG_SEL_1[15..8]        - (RW) see the description of AGG_RANGE_SEL_0
    AGG_RANG_SEL_2[23..16]       - (RW) see the description of AGG_RANGE_SEL_0
    AGG_RANG_SEL_3[31..24]       - (RW) see the description of AGG_RANGE_SEL_0

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0ARNG0_AGG_RANG_SEL_3_ADDR             BN0_WF_MIB_TOP_M0ARNG0_ADDR
#define BN0_WF_MIB_TOP_M0ARNG0_AGG_RANG_SEL_3_MASK             0xFF000000                // AGG_RANG_SEL_3[31..24]
#define BN0_WF_MIB_TOP_M0ARNG0_AGG_RANG_SEL_3_SHFT             24
#define BN0_WF_MIB_TOP_M0ARNG0_AGG_RANG_SEL_2_ADDR             BN0_WF_MIB_TOP_M0ARNG0_ADDR
#define BN0_WF_MIB_TOP_M0ARNG0_AGG_RANG_SEL_2_MASK             0x00FF0000                // AGG_RANG_SEL_2[23..16]
#define BN0_WF_MIB_TOP_M0ARNG0_AGG_RANG_SEL_2_SHFT             16
#define BN0_WF_MIB_TOP_M0ARNG0_AGG_RANG_SEL_1_ADDR             BN0_WF_MIB_TOP_M0ARNG0_ADDR
#define BN0_WF_MIB_TOP_M0ARNG0_AGG_RANG_SEL_1_MASK             0x0000FF00                // AGG_RANG_SEL_1[15..8]
#define BN0_WF_MIB_TOP_M0ARNG0_AGG_RANG_SEL_1_SHFT             8
#define BN0_WF_MIB_TOP_M0ARNG0_AGG_RANG_SEL_0_ADDR             BN0_WF_MIB_TOP_M0ARNG0_ADDR
#define BN0_WF_MIB_TOP_M0ARNG0_AGG_RANG_SEL_0_MASK             0x000000FF                // AGG_RANG_SEL_0[7..0]
#define BN0_WF_MIB_TOP_M0ARNG0_AGG_RANG_SEL_0_SHFT             0

/* =====================================================================================

  ---M0ARNG1 (0x820ED000 + 0x4BC)---

    AGG_RANG_SEL_4[7..0]         - (RW) see the description of AGG_RANGE_SEL_0
    AGG_RANG_SEL_5[15..8]        - (RW) see the description of AGG_RANGE_SEL_0
    AGG_RANG_SEL_6[23..16]       - (RW) see the description of AGG_RANGE_SEL_0
    AGG_RANG_SEL_7[31..24]       - (RW) see the description of AGG_RANGE_SEL_0

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0ARNG1_AGG_RANG_SEL_7_ADDR             BN0_WF_MIB_TOP_M0ARNG1_ADDR
#define BN0_WF_MIB_TOP_M0ARNG1_AGG_RANG_SEL_7_MASK             0xFF000000                // AGG_RANG_SEL_7[31..24]
#define BN0_WF_MIB_TOP_M0ARNG1_AGG_RANG_SEL_7_SHFT             24
#define BN0_WF_MIB_TOP_M0ARNG1_AGG_RANG_SEL_6_ADDR             BN0_WF_MIB_TOP_M0ARNG1_ADDR
#define BN0_WF_MIB_TOP_M0ARNG1_AGG_RANG_SEL_6_MASK             0x00FF0000                // AGG_RANG_SEL_6[23..16]
#define BN0_WF_MIB_TOP_M0ARNG1_AGG_RANG_SEL_6_SHFT             16
#define BN0_WF_MIB_TOP_M0ARNG1_AGG_RANG_SEL_5_ADDR             BN0_WF_MIB_TOP_M0ARNG1_ADDR
#define BN0_WF_MIB_TOP_M0ARNG1_AGG_RANG_SEL_5_MASK             0x0000FF00                // AGG_RANG_SEL_5[15..8]
#define BN0_WF_MIB_TOP_M0ARNG1_AGG_RANG_SEL_5_SHFT             8
#define BN0_WF_MIB_TOP_M0ARNG1_AGG_RANG_SEL_4_ADDR             BN0_WF_MIB_TOP_M0ARNG1_ADDR
#define BN0_WF_MIB_TOP_M0ARNG1_AGG_RANG_SEL_4_MASK             0x000000FF                // AGG_RANG_SEL_4[7..0]
#define BN0_WF_MIB_TOP_M0ARNG1_AGG_RANG_SEL_4_SHFT             0

/* =====================================================================================

  ---M0ARNG2 (0x820ED000 + 0x4C0)---

    AGG_RANG_SEL_8[7..0]         - (RW) see the description of AGG_RANGE_SEL_0
    AGG_RANG_SEL_9[15..8]        - (RW) see the description of AGG_RANGE_SEL_0
    AGG_RANG_SEL_10[23..16]      - (RW) see the description of AGG_RANGE_SEL_0
    AGG_RANG_SEL_11[31..24]      - (RW) see the description of AGG_RANGE_SEL_0

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0ARNG2_AGG_RANG_SEL_11_ADDR            BN0_WF_MIB_TOP_M0ARNG2_ADDR
#define BN0_WF_MIB_TOP_M0ARNG2_AGG_RANG_SEL_11_MASK            0xFF000000                // AGG_RANG_SEL_11[31..24]
#define BN0_WF_MIB_TOP_M0ARNG2_AGG_RANG_SEL_11_SHFT            24
#define BN0_WF_MIB_TOP_M0ARNG2_AGG_RANG_SEL_10_ADDR            BN0_WF_MIB_TOP_M0ARNG2_ADDR
#define BN0_WF_MIB_TOP_M0ARNG2_AGG_RANG_SEL_10_MASK            0x00FF0000                // AGG_RANG_SEL_10[23..16]
#define BN0_WF_MIB_TOP_M0ARNG2_AGG_RANG_SEL_10_SHFT            16
#define BN0_WF_MIB_TOP_M0ARNG2_AGG_RANG_SEL_9_ADDR             BN0_WF_MIB_TOP_M0ARNG2_ADDR
#define BN0_WF_MIB_TOP_M0ARNG2_AGG_RANG_SEL_9_MASK             0x0000FF00                // AGG_RANG_SEL_9[15..8]
#define BN0_WF_MIB_TOP_M0ARNG2_AGG_RANG_SEL_9_SHFT             8
#define BN0_WF_MIB_TOP_M0ARNG2_AGG_RANG_SEL_8_ADDR             BN0_WF_MIB_TOP_M0ARNG2_ADDR
#define BN0_WF_MIB_TOP_M0ARNG2_AGG_RANG_SEL_8_MASK             0x000000FF                // AGG_RANG_SEL_8[7..0]
#define BN0_WF_MIB_TOP_M0ARNG2_AGG_RANG_SEL_8_SHFT             0

/* =====================================================================================

  ---M0ARNG3 (0x820ED000 + 0x4C4)---

    AGG_RANG_SEL_12[7..0]        - (RW) see the description of AGG_RANGE_SEL_0
    AGG_RANG_SEL_13[15..8]       - (RW) see the description of AGG_RANGE_SEL_0
    AGG_RANG_SEL_14[23..16]      - (RW) see the description of AGG_RANGE_SEL_0
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_MIB_TOP_M0ARNG3_AGG_RANG_SEL_14_ADDR            BN0_WF_MIB_TOP_M0ARNG3_ADDR
#define BN0_WF_MIB_TOP_M0ARNG3_AGG_RANG_SEL_14_MASK            0x00FF0000                // AGG_RANG_SEL_14[23..16]
#define BN0_WF_MIB_TOP_M0ARNG3_AGG_RANG_SEL_14_SHFT            16
#define BN0_WF_MIB_TOP_M0ARNG3_AGG_RANG_SEL_13_ADDR            BN0_WF_MIB_TOP_M0ARNG3_ADDR
#define BN0_WF_MIB_TOP_M0ARNG3_AGG_RANG_SEL_13_MASK            0x0000FF00                // AGG_RANG_SEL_13[15..8]
#define BN0_WF_MIB_TOP_M0ARNG3_AGG_RANG_SEL_13_SHFT            8
#define BN0_WF_MIB_TOP_M0ARNG3_AGG_RANG_SEL_12_ADDR            BN0_WF_MIB_TOP_M0ARNG3_ADDR
#define BN0_WF_MIB_TOP_M0ARNG3_AGG_RANG_SEL_12_MASK            0x000000FF                // AGG_RANG_SEL_12[7..0]
#define BN0_WF_MIB_TOP_M0ARNG3_AGG_RANG_SEL_12_SHFT            0

#ifdef __cplusplus
}
#endif

#endif // __BN0_WF_MIB_TOP_REGS_H__
